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cologne chip hfc - s mini isdn hdlc fifo controller with s/t interface and integrated fifos data sheet july 2003
hfc-s mini cologne chip revision history date remarks july 2003 the data sheet has completely been revised. section ?processor interface modes? moved into section ?microprocessor interface?, ?list of registers? moved to the document preamble, information has been added to fifo initialization, transformer list, processor interface timings, pcm data rate restrictions, electrical character- istics, clock synchronization, cascade-connected hfc-s mini with only one quartz circuitry and the following registers: inc_res_f , ram_data , fifo , f_usage , f_fill , fif_data_noinc , f_thres , int_s1 , int_m1 , int_m2 , con_hdlc , status , mst_mode0 , mst_mode1 , mst_mode2 , st_rd_sta , st_wr_sta , clkdel . september 2001 information added to: mst_mode0 and con_hdlc register description. august 2001 chapters added: timing diagrams for motorala mode (mode2), sample circuitries. july 2001 information added to: register description. january 2001 information added to: microprocessor access, pcm / gci / iom2 timing. cologne chip ag eintrachtstrasse 113 d - 50668 k?ln germany tel.: +49 (0) 221 / 91 24-0 fax: +49 (0) 221 / 91 24-100 http://www.colognechip.com http://www.colognechip.de support@colognechip.com copyright 1994 - 2003 cologne chip ag all rights reserved the information presented can not be considered as assured characteristics. data can change without notice. parts of the information presented may be protected by patent or other rights. cologne chip products are not designed, intended, or authorized for use in any application intended to support or sustain life, or for any other application in which the failure of the cologne chip product could create a situation where personal injury or death may occur. 2of 94 data sheet july 2003
hfc-s mini cologne chip contents 1 general description 9 1.1 features ......................................... 9 1.2 block diagram ...................................... 10 1.3 applications ....................................... 10 2 pin description 11 3 functional description 14 3.1 microprocessor interface ................................ 14 3.1.1 processor interface modes ........................... 14 3.1.2 register access ................................. 14 3.2 fifos .......................................... 15 3.2.1 fifo channel operation ............................ 17 3.2.1.1 send channels (b1, b2, d and pcm transmit) ........... 17 3.2.1.2 automatically d-channel frame repetition ............. 18 3.2.1.3 fifo full condition in send channel ................. 18 3.2.1.4 receive channels (b1, b2, d and pcm or e receive) ....... 18 3.2.1.5 fifo full condition in receive channels ............... 20 3.2.2 fifo initialization ............................... 20 3.2.3 fifo reset ................................... 20 3.3 transparent mode of hfc-s mini ............................ 20 3.4 correspondency between fifos, channels and slots .............. 21 3.5 subchannel processing ................................. 26 3.6 pcm interface function ................................ 27 3.7 con?guring test loops .................................. 28 4 register description 29 4.1 fifo, interrupt, status and control registers ...................... 29 4.2 pcm/gci/iom2 bus section registers ......................... 44 4.2.1 time slots for transmit direction ........................ 44 4.2.2 time slots for receive direction ......................... 46 4.2.3 pcm data registers ............................... 48 4.2.4 con?guration and status registers ....................... 50 4.3 s/t section registers ................................... 54 4.3.1 s/t data registers ................................ 59 5 electrical characteristics 62 july 2003 data sheet 3 of 94
hfc-s mini cologne chip 6 timing characteristics 66 6.1 microprocessor access ................................. 66 6.1.1 register read access in mode 2 (motorola) and mode 3 (intel) ........ 66 6.1.2 register write access in mode 2 (motorola) and mode 3 (intel) ........ 68 6.1.3 register read access in mode 4 (intel, multiplexed) .............. 70 6.1.4 register write access in mode 4 (intel, multiplexed) .............. 71 6.2 pcm/gci/iom2 timing ................................. 72 6.2.1 master mode .................................. 73 6.2.2 slave mode ................................... 74 7 external circuitries 75 7.1 s/t interface circuitry .................................. 75 7.1.1 external receiver circuitry ........................... 75 7.1.2 external wake-up circuitry ........................... 76 7.1.3 external transmitter circuitry .......................... 77 7.1.4 s/t modules and transformers ......................... 78 7.2 oscillator circuitry for system clock .......................... 79 8 state matrices for nt and te 80 8.1 s/t interface activation / deactivation layer 1 state matrix for nt ........... 80 8.2 s/t interface activation / deactivation layer 1 state matrix for te ........... 81 9 binary organization of the frames 82 9.1 s/t frame structure ................................... 82 9.2 gci frame structure ................................... 83 10 clock synchronization 84 10.1 clock synchronization in nt-mode ........................... 84 10.2 clock synchronization in te-mode ........................... 85 10.3 multiple hfc-s mini synchronization scheme ..................... 86 11 hfc-s mini package dimensions 87 12 sample circuitries 88 12.1 s/t interface circuitry (valid in all modes) ....................... 88 12.2 hfc-s mini in mode 2 (motorola bus) ......................... 91 12.3 hfc-s mini in mode 3 (intel bus with separate address bus/data bus) ......... 92 12.4 hfc-s mini in mode 4 (intel bus with multiplexed address bus/data bus) ....... 93 4of 94 data sheet july 2003
hfc-s mini cologne chip list of figures 1 hfc-s mini block diagram ............................... 10 2 pin connection ..................................... 11 3 fifo organization ................................... 17 4 fifo data organization ................................ 19 5 fifos, channels and slots in transmit direction ................. 24 6 fifos, channels and slots in receive direction .................. 25 7 example for subchannel processing .......................... 26 8 pcm interface function block diagram ........................ 27 9 function of con_hdlc register bits 7..5 ....................... 41 10 read access in mode 2 (motorola) and mode 3 (intel) ................. 66 11 write access in mode 2 (motorola) and mode 3 (intel) ................. 68 12 read access in mode 4 (intel, multiplexed) ....................... 70 13 write access in mode 4 (intel, multiplexed) ...................... 71 14 pcm / gci / iom2 timing ................................ 72 15 external receiver circuitry ............................... 75 16 external wake-up circuitry ............................... 76 17 external transmitter circuitry .............................. 77 18 oscillator circuitry for s/t clock ............................ 79 19 cascade-connected hfc-s mini with only one quartz circuitry ............ 79 20 frame structure at reference point s and t ....................... 82 21 single channel gci format ............................... 83 22 clock synchronization in nt-mode ........................... 84 23 clock synchronization in te-mode ........................... 85 24 multiple hfc-s mini synchronization scheme ..................... 86 25 hfc-s mini package dimensions ............................ 87 26 hfc-s mini sample circuitry .............................. 88 27 hfc-s mini sample circuitry in processor mode 2 (motorola) ............. 91 28 hfc-s mini sample circuitry in processor mode 3 (intel), 1st part ........... 92 29 hfc-s mini sample circuitry in processor mode 4 (intel, multiplexed), 1st part .... 93 july 2003 data sheet 5 of 94
hfc-s mini cologne chip list of tables 2 function of the microprocessor interface control signals ................ 15 3 possible connections of fifo and channels in simple mode (sm) ........ 22 4 channel numbers on the s/t interface and pcm interface ............. 22 5 fifo to s/t channel assignment ............................ 26 6 pcm interface control options ............................. 27 7 i/o characteristics .................................... 65 8 driver capability .................................... 65 9 symbols of read accesses in figure 10 ......................... 67 10 symbols of write accesses in figure 11 ......................... 68 11 symbols of read accesses in figure 12 ......................... 70 12 symbols of write accesses in figure 13 ......................... 71 13 pcm timing values in master mode ........................... 73 14 pcm timing values in slave mode ........................... 74 15 activation / deactivation layer 1 for ?nite state matrix for nt ............. 80 16 activation / deactivation layer 1 for ?nite state matrix for te ............. 81 6of 94 data sheet july 2003
hfc-s mini cologne chip list of registers sorted by name please note ! register addresses are assigned independently for write and read access; i.e. in some cases there are different registers for write and read access with the same address. only registers with the same meaning and bitmap structure in both write and read directions are declared to be read / write. write only registers: address name page 0x26 aux1_rsl 47 0x22 aux1_ssl 45 0x27 aux2_rsl 47 0x23 aux2_ssl 45 0x24 b1_rsl 46 0x3c b1_send 60 0x20 b1_ssl 44 0x25 b2_rsl 46 0x3d b2_send 60 0x21 b2_ssl 44 0xf4 ch_mask 41 0xfc channel 42 0x00 cirm 29 0x37 clkdel 59 0xfa con_hdlc 40 0x3e d_send 61 0x0b f_cross 29 0x0d f_mode 30 0x0c f_thres 34 0x0f fifo 31 0xfb hdlc_par 39 0x0e inc_res_f 30 0x1a int_m1 38 0x1b int_m2 38 0x14 mst_mode0 50 0x15 mst_mode1 51 0x16 mst_mode2 52 0x09 ram_adr_h 31 0x08 ram_adr_l 30 0x32 sctrl_e 57 0x33 sctrl_r 57 0x31 sctrl 56 0x34 sq_send 58 0x30 st_wr_sta 55 0x1c time_sel 43 read only registers: address name page 0x3c b1_rec 59 0x3d b2_rec 60 0x16 chip_id 42 0x3e d_rec 60 0x3f e_rec 61 0x1b f_fill 35 0x1a f_usage 32 0x19 f0_cnt_h 53 0x18 f0_cnt_l 52 0x0c fif_f1 32 0x0d fif_f2 33 0x04 fif_z1 33 0x06 fif_z2 33 0x10 int_s1 36 0x11 int_s2 37 0x34 sq_rec 58 0x30 st_rd_sta 54 0x1c status 43 0x29 trxr 53 read / write registers: address name page 0x2e aux1_d 48 0x2f aux2_d 49 0x2c b1_d 48 0x2d b2_d 48 0x28 c/i 53 0x84 fif_data_noinc 32 0x80 fif_data 32 0x2a mon1_d 54 0x2b mon2_d 54 0xc0 ram_data 31 july 2003 data sheet 7 of 94
hfc-s mini cologne chip list of registers sorted by address please note ! register addresses are assigned independently for write and read access; i.e. in some cases there are different registers for write and read access with the same address. only registers with the same meaning and bitmap structure in both write and read directions are declared to be read / write. write only registers: address name page 0x00 cirm 29 0x08 ram_adr_l 30 0x09 ram_adr_h 31 0x0b f_cross 29 0x0c f_thres 34 0x0d f_mode 30 0x0e inc_res_f 30 0x0f fifo 31 0x14 mst_mode0 50 0x15 mst_mode1 51 0x16 mst_mode2 52 0x1a int_m1 38 0x1b int_m2 38 0x1c time_sel 43 0x20 b1_ssl 44 0x21 b2_ssl 44 0x22 aux1_ssl 45 0x23 aux2_ssl 45 0x24 b1_rsl 46 0x25 b2_rsl 46 0x26 aux1_rsl 47 0x27 aux2_rsl 47 0x30 st_wr_sta 55 0x31 sctrl 56 0x32 sctrl_e 57 0x33 sctrl_r 57 0x34 sq_send 58 0x37 clkdel 59 0x3c b1_send 60 0x3d b2_send 60 0x3e d_send 61 0xf4 ch_mask 41 0xfa con_hdlc 40 0xfb hdlc_par 39 0xfc channel 42 read only registers: address name page 0x04 fif_z1 33 0x06 fif_z2 33 0x0c fif_f1 32 0x0d fif_f2 33 0x10 int_s1 36 0x11 int_s2 37 0x16 chip_id 42 0x18 f0_cnt_l 52 0x19 f0_cnt_h 53 0x1a f_usage 32 0x1b f_fill 35 0x1c status 43 0x29 trxr 53 0x30 st_rd_sta 54 0x34 sq_rec 58 0x3c b1_rec 59 0x3d b2_rec 60 0x3e d_rec 60 0x3f e_rec 61 read / write registers: address name page 0x28 c/i 53 0x2a mon1_d 54 0x2b mon2_d 54 0x2c b1_d 48 0x2d b2_d 48 0x2e aux1_d 48 0x2f aux2_d 49 0x80 fif_data 32 0x84 fif_data_noinc 32 0xc0 ram_data 31 8of 94 data sheet july 2003
hfc-s mini cologne chip 1 general description the hfc-s mini is a single-chip isdn s/t hdlc basic rate controller for embedded applications. the s/t interface, hdlc controllers, fifos and a microprocessor interface are integrated in the hfc-s mini . a pcm128 / pcm64 / pcm30 interface is also implemented which can be connected to many telecom serial busses. codecs are usually connected to this interface. all isdn channels (2 b + 1 d) and the pcm interface are served fully duplex by the 8 integrated fifos. hdlc con- trollers are implemented in hardware so there is no need to implement hdlc on the host processor. 1.1 features ? single chip isdn s/t controller with b- and d-channel hdlc support ? integrated s/t interface ? full i.430 itu s/t isdn support in te and nt mode for 3.3 v and 5 v power supply ? independent read and write hdlc channels for two isdn b-channels, one isdn d-channel and one additional pcm time slot (or e-channel) ? b1- and b2-channel transparent mode independently selectable ? integrated fifos for b1-channel, b2-channel, d-channel and an additional pcm (or e-channel) channel ? fifo size: 128 bytes per channel and direction; up to 7 hdlc frames per fifo ? 56 kbit/s restricted mode for u.s. isdn lines selectable by software ? pcm128 / pcm64 / pcm30 interface con?gurable to interface mitel st tm bus (mvip tm ), siemens iom2 tm or gci tm for interface to u-chip or external codecs ? h.100 data rate supported ? microprocessor interface compatible to motorola bus and intel bus ? timer with interrupt capability ? cmos technology, 3 v . . 5 v ? pqfp 48 package july 2003 data sheet 9 of 94
hfc-s mini cologne chip 1.2 block diagram figure 1: hfc-s mini block diagram 1.3 applications the hfc-s mini can be used for all kinds of isdn equipment with isdn basic rate s/t interface. ? isdn terminal adapters (for internet access) ? isdn terminal adapters (with pots interfaces) ? isdn pabx ? isdn soho pabx (switching done by hfc-s mini ) ? isdn telephones ? isdn video conferencing equipment ? isdn dialers and lcr (least cost routers) ? isdn lan routers ? isdn protocol analyzers ? isdn smart nts 10 of 94 data sheet july 2003
hfc-s mini cologne chip 2 pin description 1 36 26 31 6 2 35 25 30 7 3 34 29 8 4 33 28 20 24 41 37 16 45 18 22 43 39 14 47 19 23 42 38 15 46 17 21 44 40 13 48 9 5 32 27 10 11 12 /rd nc r2 gnd gnd gnd /wr f1_b vdd r1 nc sync_i vdd f1_a gnd lev_r1 sync_o gnd /cs d0 stio2 tx1_hi lev_r2 /int vdd d1 stio1 /tx2_lo ale d2 f0io /tx_en a0 d3 c4io /tx1_lo /res d4 gnd tx2_hi d5 awake d6 clko d7 clki gnd adj_lev figure 2: pin connection pin interface name i/o description 1 1st function /rd i read signal from external processor (low active) 2nd function /ds i i/o data strobe 2 1st function /wr i write signal from external processor (low active) 2nd function r/w i read/write select (wr = ?0?) 3 vdd vdd (3.3v or 5v) 4 d0 ior data bus (bit 0) 5 d1 ior data bus (bit 1) 6 d2 ior data bus (bit 2) 7 d3 ior data bus (bit 3) 8 d4 ior data bus (bit 4) 9 d5 ior data bus (bit 5) 10 d6 ior data bus (bit 6) 11 d7 ior data bus (bit 7) (continued on next page) july 2003 data sheet 11 of 94
hfc-s mini cologne chip (continued from previous page) pin interface name i/o description 12 gnd gnd 13 tx2 _ hi o transmit output 2 14 /tx1 _ lo o gnd driver for transmitter 1 15 /tx _ en o transmit enable 16 /tx2 _ lo o gnd driver for transmitter 2 17 tx1 _ hi o transmit output 1 18 gnd gnd 19 vdd vdd (3.3v or 5v) 20 r2 i receive data 2 21 lev _ r2 i level detect for r2 22 lev _ r1 i level detect for r1 23 r1 i receive data 1 24 gnd gnd 25 adj _ lev o level generator 26 clki i 24.576 mhz clock input or 24.576 mhz crystal 27 clko o 24.576 mhz clock output or 24.576 mhz crystal 28 awake i awake input pin for external awake circuitry 29 gnd gnd 30 c4io iopu double bit clock 4.096 mhz / 8.192 mhz / 16.384 mhz 31 f0io iopu frame synchronization, 8 khz pulse for pcm/gci/iom2 bus frame synchronization 32 stio1 iopu pcm/gci/iom2 bus data line 1 33 stio2 iopu pcm/gci/iom2 bus data line 2 34 f1 _ a o enable signal for external codec a or c2io clock (bit clock), programmable as positive (reset default) or negative pulse 35 f1 _ b o enable signal for external codec b, programmable as positive (reset default) or negative pulse 36 nc must not be connected 38 sync _ i i 8 khz synchronization input 39 gnd gnd 40 vdd vdd (3.3v or 5v) 41 gnd gnd (continued on next page) 12 of 94 data sheet july 2003
hfc-s mini cologne chip (continued from previous page) pin interface name i/o description 42 nc must not be connected 43 sync _ o o 8 khz synchronization output 44 /int ood interrupt request for external processor (low active) 45 ale ipu address latch enable ale is also used for mode selection during reset 46 /cs ipu chip select (low active) 47 a0 i address bit 0 from external processor 48 /res istpu reset (low active) legend: i input pin o output pin io bidirectional pin ipu input pin with internal pull-up resistor of app. 100 k ? to vdd iopu bidirectional pin with internal pull-up resistor of app. 100 k ? to vdd istpu input pin with schmitt trigger characteristic and internal pull-up resistor of app. 100 k ? to vdd ior tristated during reset ood output pin with open drain nc not connected unused input pins should be connected to ground. july 2003 data sheet 13 of 94
hfc-s mini cologne chip 3 functional description 3.1 microprocessor interface the hfc-s mini has an integrated 8 bit microprocessor interface. it is compatible with motorola bus and intel bus. the different microprocessor interface modes are selected during reset by ale . in mode 2 (motorola bus mode) and mode 3 (de-multiplexed intel bus mode) pin a0 is the address input. the data bus is d7 .. d0 . in mode 4 (multiplexed intel bus mode) d[7:0] is the multiplexed address/data bus. a0 must be ?0? in this mode. 3.1.1 processor interface modes mode 2: motorola bus with control signals /cs, r/w, /ds is selected by setting ale to vdd . mode 3: intel bus with seperated address bus ( a0 ) and data bus ( d7 .. d0 ) and control signals /cs, /wr, /rd is selected by setting ale to gnd . mode 4: intel bus with multiplexed address bus and data bus with control signals /cs, /wr, /rd, ale. the ?rst rising edge on ale switches into this mode. a0 must be ?0? . ale latches the address. the multiplexed address / data bus is d7 .. d0 . in mode 4 all internal registers can be directly accessed. in mode 2 and mode 3 ?rst the address of the desired register must be written to the address with a0 = ?1? . afterwards data can be read / written from / to that register by reading / writing the address with a0 = ?0? . in mode 4 a0 must always be ?0? . 3.1.2 register access in mode 2 and mode 3 the hfc-s mini has 2 addresses. the lower address ( a0 = ?0? ) is used for data read / write. the higher address ( a0 = ?1? ) is write only and is used for register selection. registers are selected by ?rst setting a0 to ?1? and then writing the address of the desired register to the data bus d7 .. d0 . all following accesses to the hfc-s mini with a0 = ?0? are read / write operations concerning this register. in mode 4 all registers can be directly accessed by their address. the function of the control signals is shown in table 2 . except in mode 4, ale is assumed to be stable after reset. 14 of 94 data sheet july 2003
hfc-s mini cologne chip table 2: function of the microprocessor interface control signals (x = don?t care) /rd /wr /cs ale operation mode /ds r/w x x 1 x no data access all 1 1 x x no data access all 0 1 0 1 read data 2 0 0 0 1 write data 2 0 1 0 0 read data 3 1 0 0 0 write data 3 0100 ? read data 4 1000 ? write data 4 ( ? : 1-pulse latches register address) please note ! every asynchronous register read access should be done multiple times until two consecutive read accesses result in the same value. only this way it is ensured that the read bits are stable. this information applies to the following registers: f_usage ( 0x1a ), ram_data ( 0xc0 ), fif_data ( 0x80 ), fif_data_noinc ( 0x84 ), fif_f1 ( 0x0c ), fif_f2 ( 0x0d ), fif_z1 ( 0x04 ), fif_z2 ( 0x06 ), b1_d ( 0x2c ), b2_d ( 0x2d ), aux1_d ( 0x2e ), aux2_d ( 0x2f ), f0_cnt_l ( 0x18 ), f0_cnt_h ( 0x19 ), c/i ( 0x28 ), mon1_d ( 0x2a ), mon2_d ( 0x2b ), sq_rec ( 0x34 ). 3.2 fifos there is a transmit and a receive fifo with hdlc controller for each of the two b-channels, for the d-channel and for the pcm interface in the hfc-s mini . as an alternative the pcm receive controller can be used for the e-channel. every fifo has a length of 128 bytes in each direction. up to 7 frames can be stored in every fifo. the hdlc circuits are located on the s/t device side of the hfc-s mini . so always plain data is stored in the fifos. zero insertion and crc checksum processing for receive and transmit data is done by the hfc-s mini automatically. a fifo can be selected for access by writing its number in the fifo select register fifo . the fifos are ring buffers. to control them there are some counters. z 1 is the fifo input counter and z 2 is the fifo output counter. july 2003 data sheet 15 of 94
hfc-s mini cologne chip each counter points to a byte position in the sram. on a fifo input operation z 1 is incremented. on an output operation z 2 is incremented. after every pulse of the f0io signal two hdlc bytes for the b1- and the b2-channel are written into the s/t interface (fifos with even numbers) and two hdlc-bytes are read from the s/t interface (fifos with odd numbers). d-channel data is handled in a similar way but only 2 bits are processed. important ! instead of the s/t interface the pcm bus is also selectable for each b-channel (see con_hdlc register). if z 1 = z 2 the fifo is empty. additionally there are two counters f 1and f 2 for every fifo channel (3 bits for each channel). they count the hdlc frames in the fifos and form a ring buffer as z 1and z 2 do, too. f 1 is incremented when a complete frame has been received and stored in the fifo. f 2 is incre- mented when a complete frame has been read from the fifo. if f 1 = f 2 there is no complete frame in the fifo. when the /res line is active or software reset is active z 1, z 2, f 1and f 2 are all initialized to all ?1? s (so z -counters are initialized to 0x7f and f -counters are initialized to 0x07 ). the access to a fifo is selected by writing the fifo number into the fifo select register fifo . important ! fifo change, fifo reset and f 1 / f 2 incrementation: changing the fifo, reseting the fifo or incrementing the frame counters causes a short busy period of the hfc-s mini . this means an access to fifo control registers and data registers is not allowed until busy status is reset (bit 0 of s tat u s register). this has a maximum duration of 25 clock cycles (2 s). status, interrupt and control registers can be read or written at any time. important ! the counter state 0x00 of the z -counters follows counter state 0x7f in all fifos. the counter state 0x00 of the f -counters follows counter state 0x07 in all fifos. 16 of 94 data sheet july 2003
hfc-s mini cologne chip 3.2.1 fifo channel operation 3.2.1.1 send channels (b1, b2, d and pcm transmit) the send channels send data from the host bus interface to the fifo and the hfc-s mini converts the data into hdlc code and tranfers it from the fifo into the s/t or / and the pcm bus interface write registers. the hfc-s mini checks z 1and z 2. if z 1 = z 2 (fifo empty) the hfc-s mini generates a hdlc ?ag ?0111 1110? or idle pattern ?1111 1111? and sends it to the s/t device. in this case z 2 is not incremented. if also f 1 = f 2 only hdlc ?ags are sent to the s/t interface and all counters remain unchanged. if the frame counters are unequal f 2 is incremented and the hfc-s mini tries to send the next frame to the output device. after the end of a frame ( z 2 reaches z 1) it automatically generates the 16 bit crc checksum and adds the ending ?ag. if there is another frame in the fifo ( f 1 = f 2) the f 2 counter is incremented. with every byte being sent from the host bus side to the fifo, z 1 is incremented automatically. if a complete frame has been sent, f 1 must be incremented to send the next frame. if the frame counter f 1 is incremented, also the z -counters may change because z 1and z 2 are functions of f 1and f 2. so there are z 1 ( f 1 ) , z 2 ( f 1 ) , z 1 ( f 2 ) and z 2 ( f 2 ) (see figure 3 ). z1 00 z2 00 z2 02 z1 02 z1 06 z1 07 00h 02h 07h fifo memory output frame 02 frame 03 end of frame end of frame frame 06 input frame 07 f2 f1 figure 3: fifo organization z 1 ( f 1 ) is used for the frame which is just written from the microprocessor bus side. z 2 ( f 2 ) is used for the frame which is just beeing transmitted to the s/t device side of the hfc-s mini . z 1 ( f 2 ) is the end of frame pointer of the current output frame. in the send channels f 1 is only changed from the microprocessor interface side if the software driver wants to say ?end of send frame?. if bit 0 in inc_res_f register is set, the current value of z 1is stored, f 1 is incremented and z 1 is used as start address of the next frame automatically. z 1 ( f 2 ) and z 2 ( f 2 ) can not be accessed. july 2003 data sheet 17 of 94
hfc-s mini cologne chip important ! the hfc-s mini begins to transmit the bytes from a fifo at the moment the fifo is changed or the f 1 counter is incremented. also changing to the fifo that is already selected starts the transmission. so by selecting the same fifo again transmission can be started. this is required if a hdlc frame is longer than 128 bytes. 3.2.1.2 automatically d-channel frame repetition the d-channel send fifo has a special feature. if the s/t interface signals a d-channel contention before the crc is sent, the z 2 counter is set to the starting address of the current frame and the hfc-s mini tries to repeat the frame automatically. 3.2.1.3 fifo full condition in send channel there are two different fifo full conditions. the ?rst one is met when the fifo contents comes up to 7 frames. there is no possibility for the hfc-s mini to manage more hdlc frames even if the frames are very small. the driver software must check that there are never more than 7 hdlc frames in a fifo. the second limitation is the size of the fifo (128 bytes each). fifo full condition can be checked by reading the f_usage register. it shows the actually occupied fifo space in bytes. furthermore a threshold value can be set for all transmit and receive fifos in the f_thres register. then the f_fill register shows an indication of the ?lling level for each fifo. after data processing from or to a fifo, the f_fill register must be updated with a change fifo or an increment fifo counter operation. after this it takes up to 250 s until the bit value in the f_fill register of the processed fifo represents the actual state of the fifo ?lling level. 3.2.1.4 receive channels (b1, b2, d and pcm or e receive) the receive channels receive data from the s/t or pcm bus interface read registers. the data is converted from hdlc into plain data and sent to the fifo. then the data can be read via the micro- processor bus interface. the hfc-s mini checks the hdlc data coming in. if it ?nds a ?ag or more than 5 consecutive ?1? s it does not generate any output data. in this case z 1 is not incremented. proper hdlc data being received is converted by the hfc-s mini into plain data. after the ending ?ag of a frame the hfc-s mini checks the hdlc crc checksum. if it is correct one stat byte (see figure 4 ) with all ?0? s is inserted behind the crc data in the fifo. this last byte of a frame in the fifo is different from all ?0? s if there is no correct crc ?eld at the end of the frame. the ending ?ag of a hdlc-frame can also be the starting ?ag of the next frame. after a frame is received completely, f 1 is incremented by the hfc-s mini automatically and the next frame can be received. 18 of 94 data sheet july 2003
hfc-s mini cologne chip 01111110 zero-inserted data crc2 crc1 crc2 7eh hdlc-flag hdlc-frame data in send fifo data in receive fifo hdlc flag frame data data data data crc1 crc2 stat z1 (f1) stat = 00h if crc o.k. figure 4: fifo data organization after reading a frame via the microprocessor bus interface, f 2 must be incremented. if the frame counter f 2 is incremented, also the z -counters may change because z 1and z 2 are functions of f 1 and f 2. so there are z 1 ( f 1 ) , z 2 ( f 1 ) , z 1 ( f 2 ) and z 2 ( f 2 ) (see figure 3 ). z 1 ( f 1 ) is used for the frame which is just received from the s/t device side of the hfc-s mini . z 2 ( f 2 ) is used for the frame which is just beeing transmitted to the microprocessor bus interface. z 1 ( f 2 ) is the end of frame pointer of the current output frame. to calculate the length of the current receive frame the software has to evaluate z 1 ? z 2 + 1. when z 2 reaches z 1 the complete frame has been read. in the receive channels f 2 must be incremented from the microprocessor bus interface side after the software detects an end of receive frame ( z 1 = z 2) and f 1 = f 2. then the current value of z 2is stored, f 2 is incremented and z 2 is copied as start address of the next frame. if z 1 = z 2and f 1 = f 2 the fifo is totally empty. z 1 ( f 1 ) can not be accessed. important ! before reading a fifo, a change fifo operation (see also: fifo register) must be done even if the desired fifo is already selected. the change fifo operation is required to update the internal buffer of the hfc-s mini . otherwise the ?rst byte of the fifo will be taken from the internal buffer and may be invalid. july 2003 data sheet 19 of 94
hfc-s mini cologne chip 3.2.1.5 fifo full condition in receive channels because the isdn b-channels and the isdn d-channels have no hardware based ?ow control there is no possibility to stop input data if a receive fifo is full. so there is no fifo full condition implemented in the hfc-s mini .the hfc-s mini assumes that the fifos are so deep, that the host processors hardware and software is able to avoid any over?ow of the receive fifos. over?ow conditions are again more than 7 input frames or a real over?ow of the fifo because of excessive data (more than 128 bytes). because hdlc procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. the register f_fill indicates if the ?ll level of some fifos exceeds the number of bytes de?ned in the f_thres register. a byte over?ow can be avoided by polling this register. after data processing from or to a fifo, the f_fill register must be updated with a change fifo or an increment fifo counter operation. after this it takes up to 250 s until the bit value in the f_fill register of the processed fifo represents the actual state of the fifo ?lling level. the register f_usage shows the actually occupied fifo space in bytes. a byte over?ow can be avoided by polling this register. however to avoid any undetected fifo over?ows the software driver should check the number of frames in the fifo which is f 1 ? f 2. an over?ow exists if the number f 1 ? f 2 is less than the number in the last reading even if there was no reading of a frame in between. after a detected fifo over?ow condition this fifo must be reset by setting the fifo reset bit in the inc_res_f register. 3.2.2 fifo initialization all fifos are disabled after reset. to enable a fifo, at least one of the bits[4:1] of the con_hdlc register for the corresponding fifo must be set to ?1? . for d-channel fifos the inter frame ?ll bit (bit 0 of con_hdlc register) must be set to ?1? .the hdlc_par register must be set to 0x02 ( ?0000 0010? ). even for a data transmission between s/t interface and pcm interface where no fifo data is in- volved, the data transmission capability is only activated if the corresponding fifo is enabled. 3.2.3 fifo reset all counters z 1, z 2, f 1and f 2 of all fifos are initialized to all ?1? s after a reset. then the result is z 1 = z 2 = 0x7f and f 1 = f 2 = 0x07 . the same initialisation is done if the bit 3 in the cirm register is set (soft reset). single fifos can be reset by setting bit 1 of inc_res_f register. 3.3 transparent mode of hfc-s mini you can switch off hdlc operation for each b-channel independently. there is one bit for each b-channel in the con_hdlc control register. if this bit is set, data in the fifo is sent directly to the 20 of 94 data sheet july 2003
hfc-s mini cologne chip s/t or pcm bus interface and data from the s/t or pcm bus interface is sent directly to the fifo. the fifos should be empty when switching into transparent mode ( f 1 = f 2). if a send fifo channel changes to fifo empty condition no crc is generated and the last data byte in the fifo memory is repeated until there is new data. if the last data byte which was written to the selected fifo should be repeated, the last byte must be written without increment of z -counter ( fif_data_noinc register, address 84). in receive channels there is no check on ?ags or correct crcs and no status byte is added. the byte boundaries are not arbitrary like in hdlc mode where byte synchronisation is achieved with hdlc ?ags. the data is just the same as it comes from the s/t or pcm bus interface or is sent to this. send and receive transparent data can be handled in two ways. the usual way is transporting b- channel data with the lsb ?rst as it is usual in hdlc mode. the second way is sending the bytes in reverse bit order as it is usual for pwm data. so the ?rst bit is the msb. the bit order can be reversed by setting the corresponding bit in the f_cross register. 3.4 correspondency between fifos, channels and slots for the data processing of the hfc-s mini you must distinguish between fifos, channels and slots. the fifos are buffers between the microprocessor interface and the data interfaces pcm and/or s/t. the hdlc controllers are located on the non host bus side of the fifos. the channels are either mapped to the data channels on the s/t interface (then the channel selects the s/t channel as shown in table 3 ) or they can be connected to arbitrary time slots on the pcm interface. slots are 8 bit time slots on the pcm interface. the following values (registers) characterise fifos, channels and slots: fifo: fifo channel: channel slot: b1_rsl , b1_ssl , b2_rsl , b2_ssl , aux1_rsl , aux1_ssl , aux2_rsl and aux2_ssl even numbers (lsb = ?0? ) always belong to a transmit fifo, transmit channel (see table 4 ). odd numbers (lsb = ?1? ) always belong to a receive fifo, receive channel (see table 4 ). in simple mode ( f_mode register bit 7 = ?0? , sm) the channel number equals the fifo number. but it is possible to connect each fifo to a pcm time slot instead of the s/t interface in this mode (see table 3 ). in channel select mode ( f_mode register bit 7 = ?1? , csm) fifos can be associated with arbitrary channels. fifos are selected by writing their number in the fifo register. all fifos are disabled after initial- ization (reset). by setting at least one of the con_hdlc register bits 3..1to ?1? the selected fifo is enabled. the connection between a fifo and a channel can be established by the channel register for each fifo if channel select mode is enabled ( f_mode register bit 7 = ?1? , csm). otherwise the channel number equals the fifo number. july 2003 data sheet 21 of 94
hfc-s mini cologne chip table 3: possible connections of fifo and channels in simple mode (sm) fifo no. channel after reset possible connections in simple mode (sm) fifo [2..0] con_hdlc [7..5] ?000? transmit b1-channel (s/t) transmit b1-channel (s/t) transmit pcm time slot selected by b1_ssl ?001? receive b1-channel (s/t) receive b1-channel (s/t) receive pcm time slot selected by b1_rsl ?010? transmit b2-channel (s/t) transmit b2-channel (s/t) transmit pcm time slot selected by b2_ssl ?011? receive b2-channel (s/t) receive b2-channel (s/t) receive pcm time slot selected by b2_rsl ?100? transmit d-channel (s/t) transmit d-channel (s/t) transmit pcm time slot selected by aux1_ssl ?101? receive d-channel (s/t) receive d-channel (s/t) receive pcm time slot selected by aux1_rsl ?110? invalid (e is receive only) ? transmit pcm time slot selected by aux2_ssl ?111? receive e-channel (s/t) receive e-channel (s/t) receive pcm time slot selected by aux2_rsl the channels on the s/t interface (b1, b2, d and e) and pcm interface (b1, b2, aux1 and aux2) are numbered as shown in table 4 . table 4: channel numbers on the s/t interface and pcm interface channel no. isdn channel on the isdn channel on the channel [2..0] s/t interface pcm interface ?000? b1 transmit b1 transmit ?001? b1 receive b1 receive ?010? b2 transmit b2 transmit ?011? b2 receive b2 receive ?100? d transmit aux1 transmit ?101? d receive aux1 receive ?110? invalid (e is receive only) aux2 transmit ?111? e receive aux2 receive 22 of 94 data sheet july 2003
hfc-s mini cologne chip the data ?ow between the hfc part (fifos), s/t interface and pcm interface can be selected by the con_hdlc register (bits 7..5) for each fifo. the pcm time slot for b1, b2, aux1 and aux2 can be set by the time slot assigner (registers b1_rsl , b1_ssl , b2_rsl , b2_ssl , aux1_rsl , aux1_ssl , aux2_rsl and aux2_ssl ). data of a channel can furthermore be looped over the pcm interface (and the time slot assigner). july 2003 data sheet 23 of 94
hfc-s mini cologne chip channel slot fifo number channel number sub- channel processing hdlc data transparent data [t1] transmit channel for fifo [t2] bit count / start bit / mask bits for transmit channel [t3] select data flow for transmit channel [t4] select pcm slot no. for transmit channel see also: pcm interface function connect memory pcm s/t fifos figure 5: fifos, channels and slots in transmit direction [t1] in simple mode (sm) the channel number is the same as the fifo number. if channel select mode (csm) is enabled the transmit channel for a fifo can be selected by 1. writing the fifo number (0 . . 7) in the fifo register 2. writing the desired channel number ( 0..7)tothe channel register (bits 2..0) please note that transmit channels are even numbered (bit 0 of channel register = ?0? ). [t2] the bit values for the not processed bits of the transmit channel are read from the ch_mask register. the processed bits are taken from the fifo (see also section 3.5 ). please note that more than one fifo can transmit data to the same channel. this is useful to combine subchannels and transmit them in one isdn channel. [t3] data can either be transmitted to the s/t interface or the pcm interface. 1. write the fifo number ( 0..7)inthe fifo register 2. write the desired connection to the con_hdlc register bits 7..5 the con_hdlc register bits 7..5 se ttings must be the same for corresponding receive and transmit fifos. [t4] a pcm slot can be connected to a channel (see table 5 on page 26 ). the pcm slot number for a channel can be selected by writing the desired slot number to its time slot selection register as shown in table 5 . please note that the .._ssl registers are for transmit slots. 24 of 94 data sheet july 2003
hfc-s mini cologne chip channel slot fifo number channel number sub- channel processing hdlc data transparent data [r1] receive channel for fifo [r2] bit count / start bit / mask bits for receive channel [r3] select data flow for receive channel [r4] select pcm slot no. for receive channel see also: pcm interface function connect memory fifos pcm s/t figure 6: fifos, channels and slots in receive direction [r1] in simple mode (sm) the channel number is the same as the fifo number. if channel select mode (csm) is enabled the transmit channel for a fifo can be selected by 1. writing the fifo number ( 0..7)inthe fifo register 2. writing the desired channel number (0 . . 7) to the channel register (bits 2..0) please note that receive channels are odd numbered (bit 0 of channel register = ?1? ). [r2] the bit values of the not processed bits of the receive channel are ignored. the processed bits are taken from the channel (see also section 3.5 ). please note that more than one fifo can receive data from the same channel (e.g. bits 1..0 are processed by fifo 1 and bits 3..2byfifo3). thisisusefultos plit subchannels that have been combined to be transmitted in one isdn channel. [r3] data can either be received from the s/t interface or the pcm interface. 1. write the fifo number (0 . . 7) in the fifo register 2. write the desired connection to the con_hdlc register bits 7..5 the con_hdlc register bits 7..5 se ttings must be the same for corresponding receive and transmit fifos. [r4] a pcm slot can be connected to a channel (see table 5 ). the pcm slot number for a channel can be selected by writing the desired slot number to its time slot selection selection register as shown in table 5 . please note that only the .._rsl registers are for receive slots. july 2003 data sheet 25 of 94
hfc-s mini cologne chip table 5: fifo to s/t channel assignment (in simple mode the fifo number is used as channel number; in channel select mode the channel number can be selected for each fifo in the register channel.) channel no. register for ( fifo [2..0] time slot or channel [2..0] selection ?000? b1_ssl ?001? b1_rsl ?010? b2_ssl ?011? b2_rsl ?100? aux1_ssl ?101? aux1_rsl ?110? aux2_ssl ?111? aux2_rsl 3.5 subchannel processing the following example shows how subchannel processing can be con?gured by the hdlc_par reg- ister. bits are shown on the pcm interface. 0 1 2 3 4 5 6 channel 3 channel 2 channel 1 channel 0 channel 5 channel 4 (receive channels) (transmit channels) start bit = 2 bit count = 3 processed bits not processed bits (for transmit channels these bits are taken from the ch_mask register.) 7 figure 7: example for subchannel processing the start bit can be selected by bits 5 . . 3 of the hdlc_par register. the number of bits to process can be selected by bits 2..0ofthe hdlc_par register. by default ( hdlc_par = 0x00 ) all 8 bits are processed. in the given example the start bit is bit 2 and the number of bits to process is 3. the not processed bits are set to the value given in the ch_mask register. please note that the hdlc_par register settings can be different for each channel. 26 of 94 data sheet july 2003
hfc-s mini cologne chip 3.6 pcm interface function channel slot channel slot [2] stio1 output buffer enable for transmit slot [3] stio2 output buffer enable for transmit slot [4] input buffer select for receive slot a b [6] data channel select for receive slot channel connect memory data data channel stio1 stio2 [1] data channel select for transmit slot [5] loop mst internally a b figure 8: pcm interface function block diagram table 6: pcm interface control options number function b1_ssl , b2_ssl , aux1_ssl and aux2_ssl register bits [1] data channel select for transmit slot bits[4:0] are for time slot selection [2] stio1 output buffer enable for transmit slot bits[7:6] = ?10? ( stio1 output buffer enable) [3] stio2 output buffer enable for transmit slot bits[7:6] = ?11? ( stio2 output buffer enable) number function b1_rsl , b2_rsl , aux1_rsl and aux2_rsl register bits [4] input buffer select for receive slot bit 6 = ?0? (data in from stio2 [mux input b]) bit 6 = ?1? (data in from stio1 [mux input a]) [5] loop mst internally bit 6 of mst_mode1 register ?0? mux input b (normal operation) ?1? mux input a (internal loop) [6] data channel select for receive slot bits[4:0] are for time slot selection july 2003 data sheet 27 of 94
hfc-s mini cologne chip 3.7 con?guring test loops for electrical tests of layer 1 it is useful to create a s/t test loop for the b1 / b2 channel. the test loop described here transmits the data that has been received on the b1- or b2-channel of the s/t interface to the same transmit channel back on the s/t interface. to con?gure the test loop the following settings have to implemented: write 0x0f to register clkdel ( 0x37 ) // adjust the phase offset between receive and // transmit direction (the value depends on the external // circuitry). write 0x43 to register sctrl ( 0x31 )// 0x03 is to enable b1, b2 at the s/t interface for // transmission // bit 6 could be set for /tx1_lo and /tx2_lo setup // (non-capacitive line mode), this depends on the // external s/t circuitry write 0x00 to register st_rd_sta ( 0x30 ) // release s/t state machine for activation over the // s/t interface by incoming info 2 or info 4. write 0x03 to register sctrl_r ( 0x33 ) // con?gure s/t b1- and b2-channel to normal // receive operation. write 0x00 to register fifo ( 0x0f ) // select b1 transmit write 0xc4 to register con_hdlc ( 0xfa ) // con?gure transmit b1-channel for test loop write 0x01 to register fifo ( 0x0f ) // select b1 receive write 0xc4 to register con_hdlc ( 0xfa ) // con?gure receive b1-channel for test loop write 0x02 to register fifo ( 0x0f ) // select b2 transmit write 0xc4 to register con_hdlc ( 0xfa ) // con?gure transmit b2-channel for test loop write 0x03 to register fifo ( 0x0f ) // select b2 receive write 0xc4 to register con_hdlc ( 0xfa ) // con?gure receive b2-channel for test loop write 0x80 to register b1_ssl ( 0x20 ) // enable transmit channel for pcm / gci / iom2 bus, // pin stio1 is used as output, use time slot #0. write 0xc0 to register b1_rsl ( 0x24 ) // enable receive channel for pcm / gci / iom2 bus, // pin stio1 is used as input, use time slot #0. write 0x81 to register b2_ssl ( 0x21 ) // enable transmit channel for pcm / gci / iom2 bus, // pin stio1 is used as output, use transmission slot #1. write 0xc1 to register b2_rsl ( 0x25 ) // enable receive channel for pcm / gci / iom2 bus, // pin stio1 is used as input, use time slot #1. write 0x01 to register mst_mode0 ( 0x14 ) // con?gure hfc-s mini as pcm / gci / iom2 bus master. 28 of 94 data sheet july 2003
hfc-s mini cologne chip 4 register description 4.1 fifo, interrupt, status and control registers cirm (write only) 0x00 soft reset bits description 2..0 unused, must be ?0? 3 the reset is active until the bit is cleared. ?0? deactivate reset (reset default) ?1? activate reset 7..4 unused, must be ?0? f_cross (write only) 0x0b select bit order for fifo data ?0? normal bit order (lsb ?rst, reset default) ?1? reverse bit order (msb ?rst) bits description 0 b1 transmit 1 b1 receive 2 b2 transmit 3 b2 receive 4 d transmit 5 d receive 6 pcm transmit 7 pcm receive july 2003 data sheet 29 of 94
hfc-s mini cologne chip f_mode (write only) 0x0d channel select mode (csm) bits description 6..0 must be ?0? 7 enable csm inc_res_f [ fifo ] (write only) 0x0e f -counter increment and reset bits description 0 increment f -counter of selected fifo ?1? = increment this bit is automatically cleared. 1 reset selected fifo ?1? = reset fifo this bit is automatically cleared. 7..2 unused, should be ?0? ram_adr_l [ fifo ] (write only) 0x08 low byte of ram address bits description 7..0 address bits 7..0 for direct ram access 30 of 94 data sheet july 2003
hfc-s mini cologne chip ram_adr_h (write only) 0x09 high byte of ram address bits description 2..0 address bits 10..8 for direct ram access 5..3 must be ?0? 6 ?1? reset address this bit is automatically cleared. 7 ?1? increment address after each read or write access to ram_data ram_data (read / write) 0xc0 read/write ram data bits description 7..0 fifos should be disabled before accessing the ram directly. the registers ram_adr_h , ram_adr_l and ram_data can be used or direct accesses to the inter- nal fifo ram. they are normally not used. the fifos are located in the address range from 0x000 to 0x3ff .bits2..0oftheaddressselectthe fifo number, bits 1 0..4areusedtoaddressthefifodata. before reading / writing data from / to a memory region all fifos using this region must be disabled. fifo (write only) 0x0f fifo select bits description 2..0 ?000? b1 transmit ?001? b1 receive ?010? b2 transmit ?011? b2 receive ?100? d transmit ?101? d receive ?110? pcm transmit ?111? pcm receive or e receive 7..3 unused, should be ?0? july 2003 data sheet 31 of 94
hfc-s mini cologne chip f_usage [ fifo ] (read only) 0x1a fifo usage bits description 7..0 ?ll level of fifo in bytes fif_data [ fifo ] (read / write) 0x80 fifo data register bits description 7..0 read/write data from/to the fifo selected in the fifo register and increment z -counter fif_data_noinc [ fifo ] (read / write) 0x84 fifo data register bits description 7..0 read/write data from/to the fifo selected in the fifo register without incrementing z -counter fif_f1 [ fifo ] (read only) 0x0c fifo input hdlc frame counter f 1 bits description 7..0 up to 7 hdlc frames can be stored in each fifo. 32 of 94 data sheet july 2003
hfc-s mini cologne chip fif_f2 [ fifo ] (read only) 0x0d fifo output hdlc frame counter f 2 bits description 7..0 up to 7 hdlc frames can be stored in each fifo. fif_z1 [ fifo ] (read only) 0x04 fifo input counter z 1 bits description 7..0 up to 128 bytes can be stored in one fifo so the maximum value of the z 1 counter is 0x7f . fif_z2 [ fifo ] (read only) 0x06 fifo output counter z 2 bits description 7..0 up to 128 bytes can be stored in one fifo so the maximum value of the z 2 counter is 0x7f . july 2003 data sheet 33 of 94
hfc-s mini cologne chip f_thres (write only) 0x0c fifo threshold bits description 3..0 threshold for b1 transmit, b2 transmit, d transmit and pcm transmit (see also f_fill ) ?0000? 0 bytes ?0001? 8 bytes (reset default) ?0010? 16 bytes (reset default) :: ?1111? 120 bytes the corresponding bit(s) in the f_fill register are set if the number of bytes in a transmit fifo is greater or equal than this value. 7..4 threshold for b1 receive, b2 receive, d receive and pcm receive (see also f_fill ) ?0000? 0 bytes ?0001? 8 bytes (reset default) ?0010? 16 bytes (reset default) :: ?1111? 120 bytes the corresponding bit(s) in the f_fill register are set if the number of bytes in a receive fifo is greater or equal than this value. 34 of 94 data sheet july 2003
hfc-s mini cologne chip f_fill (read only) 0x1b ?0? number of bytes in the following fifos is lower than the value de?ned in the f_thres register. ?1? number of bytes in the following fifos is greater or equal than the value de?ned in the f_thres register. bits description 0 b1 transmit 1 b1 receive 2 b2 transmit 3 b2 receive 4 d transmit 5 d receive 6 pcm transmit 7 pcm receive important ! after data reading from or writing to a fifo, the f_fill register must be up- dated with a change fifo or an increment fifo counter operation. after this it takes up to 250 s until the bit value in the register f_fill of the processed fifo represents the actual state of the fifo ?lling level. july 2003 data sheet 35 of 94
hfc-s mini cologne chip int_s1 (read only) 0x10 fifo interrupt status bits description 0 b1 fifo interrupt status in transmit direction ?1? a complete frame has been transmitted, the frame counter f 2 has been incremented 1 b1 fifo interrupt status in receive direction ?1? a complete frame has been transmitted, the frame counter f 1 has been incremented 2 b2 fifo interrupt status in transmit direction ?1? a complete frame has been transmitted, the frame counter f 2 has been incremented 3 b2 fifo interrupt status in receive direction ?1? a complete frame has been transmitted, the frame counter f 1 has been incremented 4 d fifo interrupt status in transmit direction ?1? a complete frame was transmitted, the frame counter f 2 has been incremented 5 d fifo interrupt status in receive direction ?1? a complete frame was transmitted, the frame counter f 1 has been incremented 6 pcm fifo interrupt status in transmit direction ?1? a complete frame was transmitted, the frame counter f 2 has been incremented 7 pcm fifo interrupt status in receive direction ?1? a complete frame was transmitted, the frame counter f 1 has been incremented please note ! the interrupts indicated in the int_s1 register are frame interrupts which occur in hdlc mode. in transparent mode an interrupt can be generated on a regular basis. interrupt frequency can be selected in the con_hdlc register. 36 of 94 data sheet july 2003
hfc-s mini cologne chip int_s2 (read only) 0x11 interrupt status bits description 0 te/nt state machine interrupt status ?1? state of state machine changed 1 timer interrupt status ?1? timer is elapsed 2 processing/non processing transition interrupt status ?1? the hfc-s mini has changed from processing to non processing state. 3 gci i-change interrupt ?1? a different i-value on gci was detected 4 receiver ready (rxr) of monitor channel ?1? 2 monitor bytes have been received 7..5 unused, ?0? important ! reading the int_s1 or int_s2 register resets all active read interrupts in the int_s1 or int_s2 register respectively. new interrupts may occur during read. these interrupts are reported at the next read of int_s1 or int_s2 . all interrupt bits are reported regardless of the mask registers settings ( int_m1 and int_m2 ). the mask registers settings only in?uence the interrupt output condition. the interrupt output goes inactive during the read of int_s1 or int_s2 . if inter- rupts occur during this read the interrupt line goes active immediately after the read is ?nished. so processors with level or transition triggered interrupt inputs can be connected. july 2003 data sheet 37 of 94
hfc-s mini cologne chip int_m1 (write only) 0x1a interrupt mask for mask bits of this register a ?1? enables and a ?0? disables the interrupt. reset clears all bits to ?0? . bits description 0 interrupt mask for b1-channel in transmit direction 1 interrupt mask for b1-channel in receive direction 2 interrupt mask for b2-channel in transmit direction 3 interrupt mask for b2-channel in receive direction 4 interrupt mask for d-channel in transmit direction 5 interrupt mask for d-channel in receive direction 6 interrupt mask for pcm-channel in transmit direction 7 interrupt mask for pcm-channel in receive direction int_m2 (write only) 0x1b interrupt mask for mask bits of this register a ?1? enables and a ?0? disables the interrupt. reset clears all bits to ?0? . bits description 0 interrupt mask for te/nt state machine state change 1 interrupt mask for timer 2 interrupt mask for processing/non processing transition 3 interrupt mask for gci i-change 4 interrupt mask for receiver ready (rxr) of monitor channel 5 unused, must be ?0? 6 interrupt output is reversed 7 enable interrupt output 38 of 94 data sheet july 2003
hfc-s mini cologne chip hdlc_par [ fifo ] (write only) 0xfb bits description 2..0 bit count for hdlc and transparent mode (number of bits to process) ?000? process 8 bits (64 kbit/s) (reset default) ?001? process 1 bit :: ?111? process 7 bits (56 kbit/s) 5..3 start bit for hdlc and transparent mode ?000? start processing with bit 0 (reset default) :: ?111? start processing with bit 7 6 fifo loop ?0? normal operation (reset default) ?1? repeat current frame 7 invert data enable/disable ?0? normal read/write data (reset default) ?1? invert data important ! for normal b-channel operation, the hdlc_par register must be set to 0x00 . to use 56 kbit/s restricted mode the hdlc_par register must be set to 0x07 for b-channels. for d-channels the hdlc_par register must be set to 0x02 . july 2003 data sheet 39 of 94
hfc-s mini cologne chip con_hdlc [ fifo ] (write only) 0xfa bits description 0 inter frame ?ll ?0? write hdlc ?ags 0x7e as inter frame ?ll (reset default) ?1? write all ?1? s as inter frame ?ll (must be set for d-channel) 1 hdlc mode/transparent mode select ?0? hdlc mode (reset default) ?1? transparent mode select if bits 3..1 are ?000? the fifo is disabled (reset default). 3..2 transparent mode interrupt frequency select ?00? every 8 bytes ?01? every 16 bytes ?10? every 32 bytes ?11? every 64 bytes in hdlc mode, set this bitmap = 0 to enable the fifo. 4 must be ?0? 7..5 select data ?ow for selected fifo b1-channel (fifo0 and fifo1): bit 5: ?0? fifo1 b1-s/t ?1? fifo1 b1-pcm bit 6: ?0? b1-s/t fifo0 ?1? b1-s/t b1-pcm bit 7: ?0? b1-pcm fifo0 ?1? b1-pcm b1-s/t b2-channel (fifo2 and fifo3): bit 5: ?0? fifo3 b2-s/t ?1? fifo3 b2-pcm bit 6: ?0? b2-s/t fifo2 ?1? b2-s/t b2-pcm bit 7: ?0? b2-pcm fifo2 ?1? b2-pcm b2-s/t d-channel and pcm (fifo4 and fifo5): bit 5: ?0? fifo5 d-s/t ? ?1? fifo5 aux1 bit 6: ?0? d-s/t fifo4 ?1? d-s/t aux1 bit 7: ?0? aux1 fifo4 ?1? aux1 d-s/t e-channel and pcm (fifo6 and fifo7): bit 5: ?0? fifo7 e-s/t ?1? fifo7 aux2 bit 6: ?0? e-s/t fifo6 ?1? e-s/t aux2 bit 7: ?0? aux2 fifo6 ?1? aux2 e-s/t ? : (not available if mst_mode1 [7] is set) con_hdlc register bits[7:5] must be the same for corresponding receive and transmit fifos. 40 of 94 data sheet july 2003
hfc-s mini cologne chip please note ! in any case the fifo must be enabled to activate the data transmission selected with bits 7..5ofthe con_hdlc register. important ! fifo5 for the d-channel does not work properly if gci mode is selected (bit 7 of mst_mode1 = ?1? ). in this case, the aux2 receive time slot can be con?gured to the receive time slot 3 which is related to fifo 7 in this case for d-channel receive ( hdlc_par = 0x02 and con_hdlc = 0x25 ). bit 6 bit 7 bit 5 1 0 1 0 1 0 hfc pcm s/t transmit fifo receive fifo figure 9: function of con_hdlc register bits 7 . . 5 ch_mask [ fifo ] (write only) 0xf4 bit value for not processed bits of a channel. all not processed bits of a channel are set to the value de?ned in this register. bits description 7..0 mask value july 2003 data sheet 41 of 94
hfc-s mini cologne chip channel [ fifo ] (write only) 0xfc link selected fifo to isdn channel (only in channel select mode, see f_mode register) bits description 2..0 link fifo to s/t channel ?000? b1-transmit ?001? b1-receive ?010? b2-transmit ?011? b2-receive ?100? d-transmit ?101? d-receive ?110? invalid (e is receive only) ?111? e-receive 7..3 unused, must be ?0? chip_id (read only) 0x16 chip identi?cation bits description 3..0 unused, ?0? 7..4 ?0101? hfc-s mini 42 of 94 data sheet july 2003
hfc-s mini cologne chip status (read only) 0x1c bits description 0 busy/nobusy status ?1? the hfc-s mini is busy after initializing, reset fifo, increment f or change fifo ?0? the hfc-s mini is not busy, all accesses are allowed note: accesses to fifo registers are not allowed during busy period. 1 processing/non processing status ?1? the hfc-s mini is in processing phase (every 125 s) ?0? the hfc-s mini is not in processing phase 2 unused, ?0? 3 awake input signal 4 sync_i input signal 5 unused, ?0? 6 an interrupt (with enabled mask bit) indicated in the int_s2 register has occured 7 frame interrupt with enabled mask bit has occured (any fifo interrupt) all masked b-, d- and pcm-channel interrupts are ?ored? (see register int_s1 ) reading the s tat u s register clears no bit. time_sel (write only) 0x1c select interrupt frequency of timer interrupt bits description 3..0 ?0000? every 250 s ?0001? every 500 s ?0010? every 1 ms ?0011? every 2 ms ?0100? every 4 ms ?0101? every 8 ms ?0110? every 16 ms ?0111? every 32 ms ?1000? every 64 ms ?1001? every 128 ms ?1010? every 256 ms ?1011? every 512 ms ?1100? every 1024 ms ?1101? every 2048 ms ?1110? every 4096 ms ?1111? every 8192 ms 7..4 unused, must be ?0? july 2003 data sheet 43 of 94
hfc-s mini cologne chip 4.2 pcm/gci/iom2 bus section registers 4.2.1 time slots for transmit direction b1_ssl (write only) 0x20 bits description 4..0 select pcm/gci/iom2 bus transmission slot (0..31, 32..63, 64..95, 96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio1 output ?1? stio2 output 7 select pcm/gci/iom2 bus data lines ?0? stio1 output ?1? stio2 output b2_ssl (write only) 0x21 bits description 4..0 select pcm/gci/iom2 bus transmission slot (0..31, 32..63, 64..95, 96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio1 output ?1? stio2 output 7 transmit channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable 44 of 94 data sheet july 2003
hfc-s mini cologne chip aux1_ssl (write only) 0x22 bits description 4..0 select pcm/gci/iom2 bus transmission slot (0..31, 32..63, 64..95, 96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio1 output ?1? stio2 output 7 transmit channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable aux2_ssl (write only) 0x23 bits description 4..0 select pcm/gci/iom2 bus transmission slot (0..31, 32..63, 64..95, 96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio1 output ?1? stio2 output 7 transmit channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable important ! enabling more than one channel on the same slot causes unde?ned output data. july 2003 data sheet 45 of 94
hfc-s mini cologne chip 4.2.2 time slots for receive direction b1_rsl (write only) 0x24 bits description 4..0 select pcm/gci/iom2 bus receive slot (0..31, 32..63, 64..95,96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio2 is input ?1? stio1 is input 7 receive channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable b2_rsl (write only) 0x25 bits description 4..0 select pcm/gci/iom2 bus receive slot (0..31, 32..63, 64..95,96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio2 is input ?1? stio1 is input 7 receive channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable 46 of 94 data sheet july 2003
hfc-s mini cologne chip aux1_rsl (write only) 0x26 bits description 4..0 select pcm/gci/iom2 bus receive slot (0..31, 32..63, 64..95,96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio2 is input ?1? stio1 is input 7 receive channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable aux2_rsl (write only) 0x27 bits description 4..0 select pcm/gci/iom2 bus receive slot (0..31, 32..63, 64..95,96..127, see mst_mode2 register bits 5..4) 5 unused 6 select pcm/gci/iom2 bus data lines ?0? stio2 is input ?1? stio1 is input 7 receive channel enable for pcm/gci/iom2 bus ?0? disable (reset default) ?1? enable july 2003 data sheet 47 of 94
hfc-s mini cologne chip 4.2.3 pcm data registers b1_d (read / write) 0x2c bits description 7..0 read/write data registers for selected time slot data b2_d (read / write) 0x2d bits description 7..0 read/write data registers for selected time slot data aux1_d (read / write) 0x2e bits description 7..0 read/write data registers for selected time slot data 48 of 94 data sheet july 2003
hfc-s mini cologne chip aux2_d (read / write) 0x2f bits description 7..0 read/write data registers for selected time slot data all pcm data registers are read / written automatically by the hdlc fifo controller (hfc) or pcm controller and need not be accessed by the user. to read / write data the fifo registers should be used. please note ! auxiliary channel handling to support an automatic codec to codec connection aux1_d and aux2_d can be set into mirror mode. in this case, if the data registers aux1_d and aux2_d are not overwritten, the transmisson slots aux1_ssl and aux2_ssl mirror the data received in aux1_rsl and aux2_rsl slots. this is useful for an internal connection between two codecs. this mirroring is enabled by setting bits 1..0in mst_mode1 register. july 2003 data sheet 49 of 94
hfc-s mini cologne chip 4.2.4 con?guration and status registers mst_mode0 (write only) 0x14 bits description 0 pcm/gci/iom2 bus mode ?0? slave (reset default) ( c4io and f0io are inputs) ?1? master ( c4io and f0io are outputs) 1 polarity of c4io and c2o clock ?0? f0io is sampled on negative clock transition ?1? f0io is sampled on positive clock transition 2 polarity of f0io signal ?0? f0io positive pulse ?1? f0io negative pulse 3 duration of f0io signal ?0? f0io active for one c4io clock (244 ns at 2 mbit/s) (reset default) ?1? f0io active for two c4io clocks (488 ns at 2 mbit/s) 5..4 time slot for codec-a signal f1_a ?00? b1 receive slot ?01? b2 receive slot ?10? aux1 receive slot ?11? signal c2o. pin f1_a (c2o is 1/2 c4io ) 7..6 time slot for codec-b signal f1_b ?00? b1 receive slot ?01? b2 receive slot ?10? aux1 receive slot ?11? aux2 receive slot the pulse shape and polarity of the codec signals f1_a and f1_b is the same as the pulse shape of the f0io signal. the polarity of c2o can be changed by bit 1. /res clears registers mst_mode0 , mst_mode1 and mst_mode2 to all ?0? s. important ! there is always a clock signal required at the pins c4io and f0io . if no external clock source is connected to these pins (pcm slave mode), bit 0 of mst_mode0 must be set for pcm master mode. 50 of 94 data sheet july 2003
hfc-s mini cologne chip mst_mode1 (write only) 0x15 bits description 0 enable/disable aux1 channel mirroring ?0? disable aux1 channel data mirroring (reset default) ?1? mirror aux1 receive to aux1 transmit 1 enable/disable aux2 channel mirroring ?0? disable aux2 channel data mirroring (reset default) ?1? mirror aux2 receive to aux2 transmit 3..2 dpll adjust speed ?00? c4io clock is adjusted in the last time slot of mst frame 4 times by one half clock cycle of clki ?01? c4io clock is adjusted in the last time slot of mst frame 3 times by one half clock cycle of clki ?10? c4io clock is adjusted in the last time slot of mst frame twice by one half clock cycle of clki ?11? c4io clock is adjusted in the last time slot of mst frame once by one half clock cycle of clki 5..4 pcm data rate ?00? 2 mbit/s (pcm30) ?01? 4 mbit/s (pcm64), long f0io signal required ( > 170 ns, bit 3 of mst_mode0 must be set) ?10? 8 mbit/s (pcm128), only in pcm slave mode and with long f0io signal ( > 170 ns, bit 3 of mst_mode0 must be set) ?11? unused 6 mst test loop when set mst output data is looped to the mst inputs. 7 enable gci/iom2 write slots ?0? disable pcm/gci/iom2 write slots; slot #2 and slot #3 may be used for normal data ?1? enables slot #2 and slot #3 as master, d- and c/i-channel important ! as the f0io pulse must be 170 ns at least in all cases where the s/t interface is used, the following restrictions must be ful?lled: ? in master mode bit 3 of mst_mode0 must be ?1? at 4 mbit/s. a data rate of 8 mbit/s is not available. ? in slave mode any data rate of mst_mode1 [4..5] is selectable if f0io > 170 ns (bit 3 of mst_mode0 = ?1? ). july 2003 data sheet 51 of 94
hfc-s mini cologne chip mst_mode2 (write only) 0x16 bits description 0 ?1? generate frame signal for oki tm codecs on f1_a 1 ?1? generate frame signal for oki tm codecs on f1_b 2 select pcm dpll synchronization source ?0? s/t receive frame (only in te mode and valid frame synchronization (f6 or f7) a synchronization signal is generated) ?1? sync_i input 8 khz 3 select sync_o output ?0? s/t receive frame 8 khz (only in te mode and valid frame synchronization (f6 or f7) a synchronization signal is generated) ?1? sync_i is connected to sync_o 5..4 pcm/gci/iom2 slot select for higher data rates ?00? slots 31..0 accessable ?01? slots 63..32 accessable ?10? slots 95..64 accessable ?11? slots 127..96 accessable 6 this bit is only valid if bit 7 is set. ?0? pcm frame time is reduced as selected by bits 3..2 of the mst_mode1 register ?1? pcm frame time is increased as selected by bits 3..2 of the mst_mode1 register 7 ?0? normal operation ?1? enable pcm pll adjust according to bit 6 if no synchronization source is available. this is used to synchronize by software. f0_cnt_l (read only) 0x18 f0io pulse count bits description 7..0 16 bit 125 s time counter (low byte) 52 of 94 data sheet july 2003
hfc-s mini cologne chip f0_cnt_h (read only) 0x19 f0io pulse count bits description 7..0 16 bit 125 s time counter (high byte) c/i (read / write) 0x28 c/i channel data of gci bits description 3..0 on read: indication on write: command 7..4 unused trxr (read only) 0x29 bits description 0 ?1? monitor receiver ready (2 monitor bytes have been received) 1 ?1? monitor transmitter ready writing on mon2_d starts transmisssion and resets this bit. 5..2 reserved 6 value of stio2 input pin 7 value of stio1 input pin july 2003 data sheet 53 of 94
hfc-s mini cologne chip mon1_d (read / write) 0x2a bits description 7..0 ?rst monitor byte mon2_d (read / write) 0x2b bits description 7..0 second monitor byte 4.3 s/t section registers st_rd_sta (read only) 0x30 s/t interface state register bits description 3..0 binary value of actual state (nt: gx, te: fx) 4 frame synchronization ( ?1? = synchronized) 5 ?1? timer t2 expired (nt mode only) 6 ?1? receiving info0 7 ?1? in nt mode: transition from g2 to g3 is allowed. 54 of 94 data sheet july 2003
hfc-s mini cologne chip st_wr_sta (write only) 0x30 s/t interface state register bits description 3..0 set new state xxxx (bit 4 must also be set to load the state). 4 ?1? loads the prepared state (bit 3..0) and stops the state machine.this bit needs to be set for a minimum period of 5.21 s and must be cleared by software (reset default). ?0? enables the state machine. after writing an invalid state the state machine goes to deactivated state (g1, f2) 6..5 ?00? no operation ?01? no operation ?10? start deactivation ?11? start activation the bits are automatically cleared after activation/deactivation. 7 ?0? no operation ?1? in nt mode: allows transition from g2 to g3. this bit is automatically cleared after the transition. important ! the s/t state machine is stuck to ?0? after a reset. in this state the hfc-s mini sends no signal on the s/t line and it is not possible to activate it by incoming infox. writing a ?0? to bit 4 of the st_wr_sta register restarts the state machine. nt mode: the nt state machine does not change automatically from g2 to g3 if the te side sends info3 frames. this transition must be activated each time by bit 7 of the st_wr_sta register or by setting bit 0 of the sctrl_e register. july 2003 data sheet 55 of 94
hfc-s mini cologne chip sctrl (write only) 0x31 bits description 0 ?0? b1 send data disabled (permanent ?1? sent in activated states, reset default) ?1? b1 data enabled 1 ?0? b2 send data disabled (permanent ?1? sent in activated states, reset default) ?1? b2 data enabled 2 s/t interface mode ?0? te mode (reset default) ?1? nt mode 3 d-channel priority ?0? high priority 8/9 (reset default) ?1? low priority 10/11 4 s/q bit transmission ?0? s/q bit disable (reset default) ?1? s/q bit and multiframe enable 5 ?0? normal operation (reset default) ?1? send 96 khz transmit test signal (alternating zeros) 6 /tx1_lo and /tx2_lo line setup this bit must be con?gured depending on the used s/t module and circuitry to match the 400 ms pulse mask test. ?0? capacitive line mode (reset default) ?1? non capacitive line mode 7 power down ?0? normal operation, oscillator active (reset default) ?1? power down, oscillator stopped oscillator is restarted when awake input becomes ?1? or on any write access to the hfc-s mini . 56 of 94 data sheet july 2003
hfc-s mini cologne chip sctrl_e (write only) 0x32 bits description 0 force g2 to g3 automatic transition from g2 to g3 without setting bit 7 of st_wr_sta register 1 must be ?0? 2 d reset ?0? normal operation (reset default) ?1? d bits are forced to ?1? 3 d_u enable ?0? normal operation (reset default) ?1? d-channel is always send enabled regardless of e receive bit 4 force e = ?0? (nt mode) ?0? normal operation (reset default) ?1? e-bit send is forced to ?0? 6..5 must be ?0? 7 ?1? swap b1- and b2-channels in the s/t interface sctrl_r (write only) 0x33 bits description 0 b1-channel receive enable 1 b2-channel receive enable ?0? b receive bits are forced to ?1? ?1? normal operation 7..2 unused july 2003 data sheet 57 of 94
hfc-s mini cologne chip sq_rec (read only) 0x34 bits description 3..0 te mode: s bits (bit 3 = s1, bit 2 = s2, bit 1 = s3, bit 0 = s4) nt mode: q bits (bit 3 = q1, bit 2 = q2, bit 1 = q3, bit 0 = q4) 4 ?1? a complete s or q multiframe has been received reading sq_rec clears this bit. 6..5 not de?ned 7 ?1? ready to send a new s or q multiframe writing to sq_send clears this bit. sq_send (write only) 0x34 bits description 3..0 te mode: q bits (bit 3 = q1, bit 2 = q2, bit 1 = q3, bit 0 = q4 nt mode: s bits (bit 3 = s1, bit 2 = s2, bit 1 = s3, bit 0 = s4) 7..4 not de?ned 58 of 94 data sheet july 2003
hfc-s mini cologne chip clkdel (write only) 0x37 bits description 3..0 te: 4 bit delay value to adjust the 2 bit time delay between receive and transmit direction. the delay of the external s/t interface circuit can be compensated. the lower the value the smaller the delay between receive and transmit direction. nt: data sample point. the lower the value the earlier the input data is sampled. the step size is 163 ns. 6..4 nt mode only early edge input data shaping low pass characteristic of extended bus con?gurations can be compensated. the lower the value the earlier input data pulse is sampled. no compensation means a value of 6 ( ?110? ). the step size is 163 ns. 7 unused please note ! the register clkdel is not initialized with a ?0? after reset. the register should be initialized as follows before activating the te / nt state machine: te mode: 0x0d .. 0x0f ( 0x0f for s/t interface circuitry shown on page 75 ) nt mode: 0x6c 4.3.1 s/t data registers b1_rec (read only) 0x3c bits description 7..0 b1-channel receive register july 2003 data sheet 59 of 94
hfc-s mini cologne chip b1_send (write only) 0x3c bits description 7..0 b1-channel transmit register b2_rec (read only) 0x3d bits description 7..0 b2-channel receive register b2_send (write only) 0x3d bits description 7..0 b2-channel transmit register d_rec (read only) 0x3e bits description 7..0 d-channel receive register 60 of 94 data sheet july 2003
hfc-s mini cologne chip d_send (write only) 0x3e bits description 7..0 d-channel transmit register e_rec (read only) 0x3f bits description 7..0 e-channel receive register all s/t data registers are read / written automatically by the hdlc fifo controller (hfc) or pcm controller and need not be accessed by the user. to read / write data the fifo registers should be used. july 2003 data sheet 61 of 94
hfc-s mini cologne chip 5 electrical characteristics absolute maximum ratings parameter symbol min. max. power supply v dd ? 0 . 3v + 7 . 0v input voltage v i ? 0 . 3v v cc + 0 . 3v output voltage v o ? 0 . 3v v cc + 0 . 3v operating temperature t opr ? 10 ? c + 85 ? c storage temperature t stg ? 40 ? c + 125 ? c recommended operating conditions parameter symbol min. typ. max conditions power supply v dd 3 . 0v 3 . 3v 3 . 6v v dd = 3 . 3v 4 . 75 v 5 v 5 . 25 v v dd = 5v operating temperature t opr 0 ? c + 70 ? c supply current f clk = 24 . 576 mhz normal i dd 12 ma v dd = 3 . 3 v, running oscillator 24 ma v dd = 5 v, running oscillator power down 1 ma v dd = 3 . 3 v, oscillator stopped 2ma v dd = 5 v, oscillator stopped 62 of 94 data sheet july 2003
hfc-s mini cologne chip electrical characteristics for 3.3 v power supply (ttl level) v dd = 3 . 0v to 3 . 6v , t opr = 0 ? c to + 70 ? c parameter symbol min. typ. max low input voltage v il 0.5 v high input voltage v ih 1.5 v low output voltage v ol 0.4 v high output voltage v oh 2.4 v v dd schmitt trigger, positive-going threshold vt+ 1.3 v schmitt trigger, negative-going threshold vt- 0.5 v electrical characteristics for 3.3 v power supply (cmos level) v dd = 3 . 0v to 3 . 6v , t opr = 0 ? c to + 70 ? c parameter symbol min. typ. max low input voltage v il 1.0 v high input voltage v ih 2.0 v low output voltage v ol 0.4 v high output voltage v oh 2.4 v v dd schmitt trigger, positive-going threshold vt+ 2.0 v schmitt trigger, negative-going threshold vt- 1.0 v july 2003 data sheet 63 of 94
hfc-s mini cologne chip electrical characteristics for 5 v power supply (ttl level) v dd = 4 . 75 v to 5 . 25 v , t opr = 0 ? c to + 70 ? c parameter symbol min. typ. max low input voltage v il 0.8 v high input voltage v ih 2.0 v low output voltage v ol 0.4 v high output voltage v oh 2.4 v schmitt trigger, positive-going threshold vt+ 2.0 v schmitt trigger, negative-going threshold vt- 0.8 v electrical characteristics for 5 v power supply (cmos level) v dd = 4 . 75 v to 5 . 25 v , t opr = 0 ? c to + 70 ? c parameter symbol min. typ. max low input voltage v il 1.5 v high input voltage v ih 3.5 v low output voltage v ol 0.4 v high output voltage v oh 2.4 v schmitt trigger, positive-going threshold vt+ 4.0 v schmitt trigger, negative-going threshold vt- 1.0 v 64 of 94 data sheet july 2003
hfc-s mini cologne chip table 7: i/o characteristics input interface level /rd cmos /wr cmos /cs cmos, internal pull-up resistor ale cmos, internal pull-up resistor a0 cmos d7 .. d0 cmos clki cmos awake cmos c4io ttl schmitt trigger, internal pull-up resistor f0io cmos, internal pull-up resistor stio1 , stio2 cmos, internal pull-up resistor /res cmos schmitt trigger, internal pull-up resistor table 8: driver capability low high output 0.4 v v dd ? 0 . 8 v d7 .. d0 4ma 2ma c4io 8ma 4ma f0io 8ma 4ma stio1 , stio2 8ma 4ma f1_a , f1_b 4ma 2ma /int 4ma july 2003 data sheet 65 of 94
hfc-s mini cologne chip 6 timing characteristics 6.1 microprocessor access 6.1.1 register read access in mode 2 (motorola) and mode 3 (intel) a0 d[7:0] /ds+/cs r/w /wr+/cs /rd+/cs address data data address write data read in mode 2 only in mode 3 only data read (motorola): (intel): t rd t rdmin t ah t ah t rws t rws t rwh t rwh t as t wra t dwrs t dwrh t wra t as t rdmin t as t ah t rd t rws t rwh t cycle t rd t drdz t drdh t rd t drdz t drdh figure 10: read access in mode 2 (motorola) and mode 3 (intel) t clki is the clki clock period which is normally 40.69 ns (24.576 mhz system clock). important ! all read accesses with register address bit d[7] = ?1? (registers fif_data , fif_data_noinc and ram_data ) have a cycle time t cy cle 6 t clki between two consecutive of t rd . hint ! if the same register as in the last register read / write access is accessed the register address write is not required. 66 of 94 data sheet july 2003
hfc-s mini cologne chip table 9: symbols of read accesses in figure 10 symbol min / ns max / ns characteristic t as 10 a0 valid to /ds+/cs (/wr+/cs) setup time t ah 10 address hold time after /ds+/cs (/wr+/cs) t wra 20 write time for address write t dw rs 30 write data setup time to /ds+/cs (/wr+/cs) t dw rh 10 write data hold time from /ds+/cs (/wr+/cs) t rd read time: 2 t clki d[7] = ?0? (address range 0 ... 0x7f : normal register access) 20 d[7,6] = ?10? (address range 0x80 ... 0xbf : fifo data access) 6 t clki d[7,6] = ?11? (address range 0xc0 ... 0xff : direct internal ram access) ? t cy cle /ds+/cs (/rd+/cs) to next end of data access d[7] = ?0? (address range 0 ... 0x7f : normal register access) 6 t clki d[7,6] = ?10? (address range 0x80 ... 0xbf : fifo data access) 6 t clki d[7,6] = ?11? (address range 0xc0 ... 0xff : direct internal ram access) ? t drdz 3 /ds+/cs (/rd+/cs) to data buffer turn on time t drdh 2 15 /ds+/cs (/rd+/cs) to data buffer turn off time t rw s 2 r/w setup time to /ds+/cs t rw h 2 r/w hold time after /ds+/cs ( ? : normally this time needs not to be matched because a direct ram access is not needed.) july 2003 data sheet 67 of 94
hfc-s mini cologne chip 6.1.2 register write access in mode 2 (motorola) and mode 3 (intel) a[7:0] d[7:0] /ds+/cs r/w /wr+/cs /rd address data data permanently high address write data write in mode2 only in mode 3 only (motorola): (intel): data write t wra t wr t ah t ah t dwrh t rws t rws t rwh t rwh t dwrs t dwrs t wra t wr t dwrh t as t as t dwrs t dwrh t as t ah t wr t idle t wr t rws t rwh figure 11: write access in mode 2 (motorola) and mode 3 (intel) table 10: symbols of write accesses in figure 11 symbol min / ns max / ns characteristic t as 10 a0 valid to /ds+/cs (/wr+/cs) setup time t ah 10 address hold time after /ds+/cs (/wr+/cs) t wra 20 write time for address write t dw rs 20 write data setup time to /ds+/cs (/wr+/cs) t dw rh 10 write data hold time from /ds+/cs (/wr+/cs) t wr 20 write time t idle 5 t clki /ds+/cs (/wr+/cs) high time between two data accesses t rw s 2 r/w setup time to /ds+/cs t rw h 2 r/w hold time after /ds+/cs t clki is the clki clock period which is normally 40.69 ns (24.576 mhz system clock). 68 of 94 data sheet july 2003
hfc-s mini cologne chip important ! all write accesses with register address bit d[7] = ?1? (registers fif_data , fif_data_noinc , ram_data , ch_mask , con_hdlc , hdlc_par and channel ) have a idle time t idle 5 t clki between of t wr and the next of t wr . hint ! if the same register as in the last register read / write access is accessed, the reg- ister address write is not required. july 2003 data sheet 69 of 94
hfc-s mini cologne chip 6.1.3 register read access in mode 4 (intel, multiplexed) d[7:0] ale /rd+/cs /wr address data data permanently high address write data read data read t as t ah t ale t drdz t drdh t rdmin t rdmin t drdz t drdh t rd t rd t cycle t alel figure 12: read access in mode 4 (intel, multiplexed) table 11: symbols of read accesses in figure 12 symbol min / ns max / ns characteristic t ale 10 address latch time t alel 0ale to /rd+/cs t as 10 address valid to ale setup time t ah 10 address hold time after ale t drdz 3 /rd+/cs to data buffer turn on time t drdh 2 15 /rd+/cs to data buffer turn off time t rd read time: 2 t clki d[7] = ?0? (address range 0 ... 0x7f : normal register access) 20 d[7,6] = ?10? (address range 0x80 ... 0xbf : fifo data access) 5 t clki d[7,6] = ?11? (address range 0xc0 ... 0xff : direct internal ram access) ? t cy cle cycle time between two consecutive /rd+/cs d[7] = ?0? (address range 0 ... 0x7f : normal register access) 6 t clki d[7,6] = ?10? (address range 0x80 ... 0xbf : fifo data access) 6 t clki d[7,6] = ?11? (address range 0xc0 ... 0xff : direct internal ram access) ? ( ? : normally this time needs not to be matched because a direct ram access is not needed.) t clki is the clki clock period which is normally 40.69 ns (24.576 mhz system clock). important ! a0 must be ?0? during the whole register read cycle. it should be connected to gnd . 70 of 94 data sheet july 2003
hfc-s mini cologne chip 6.1.4 register write access in mode 4 (intel, multiplexed) d[7:0] ale /wr+/cs /rd address data data permanently high address write data write data write t wr t wr t ale t as t ah t dwrh t dwrs t dwrs t dwrh t idle t alel figure 13: write access in mode 4 (intel, multiplexed) table 12: symbols of write accesses in figure 13 symbol min / ns max / ns characteristic t ale 10 address latch time t alel 0ale to /wr+/cs t as 10 address valid to ale setup time t ah 10 address hold time after /wr+/cs t dw rs 20 write data setup time to /wr+/cs t dw rh 10 write data hold time from /wr+/cs t wr 20 write time t idle /wr+/cs high time d[7] = ?0? (address range 0 ... 0x7f : normal register access) 5 t clki d[7,6] = ?10? (address range 0x80 ... 0xbf : fifo data access) 5 t clki d[7,6] = ?11? (address range 0xc0 ... 0xff : direct internal ram access) ? ( ? : normally this time needs not to be matched because a direct ram access is not needed.) t clki is the clki clock period which is normally 40.69 ns (24.576 mhz system clock). important ! a0 must be ?0? during the whole register read cycle. it should be connected to gnd . july 2003 data sheet 71 of 94
hfc-s mini cologne chip 6.2 pcm/gci/iom2 timing t f t d t c2h t c4p t stod4 t stod2 t stih c2o on f1_a stio1/2 (input) stio1/2 (output) f0io f1_a / f1_b **) f1_a / f1_b ***) *) *) c4io t f0ih t f0iw t f0is t f0icycle t f0icycle t stis t c4h t c4l t c2l t - 1 bit cell c2p figure 14: pcm / gci / iom2 timing *) f0io starts one c4io clock earlier if bit 3 in mst_mode0 register is set. if this bit is set f0io is also awaited one c4io clock cycle earlier. **) if bit 0 (or bit 1) of the mst_mode2 register is set to ?1? a frame signal for oki tm codecs is generated on f1_a (or f1_b ). the c2o clock on f1_a is not available if bit 0 of the mst_mode2 register is set. ***) if bit 0 (or bit 1) of the mst_mode2 register is cleared to ?0? f1_a (or f1_b ) is a codec enable signal with the same pulse shape and timing as the f0io signal. if bits 5..4of mst_mode0 are ?11? f1_a is c2o clock. 72 of 94 data sheet july 2003
hfc-s mini cologne chip 6.2.1 master mode to con?gure the hfc-s mini as pcm / gci / iom2 bus master bit 0 of the mst_mode0 register must be set. in this case c4io and f0io are outputs. the pcm bit rate is con?gured by bits 5..4 of the mst_mode1 register. table 13: pcm timing values in master mode symbol characteristics min. typ. max. t c for 2 mb/s (pcm30) 122.07 ns for 4 mb/s (pcm64) 61.035 ns for 8 mb/s (pcm128) 30.518 ns t c 4 p clock c4io period ? 1 , ? 2 2 t c ? 26 ns 2 t c 2 t c + 26 ns t c 4 h clock c4io high width ? 1 , ? 2 t c ? 26 ns t c t c + 26 ns t c 4 l clock c4io low width ? 1 , ? 2 t c ? 26 ns t c t c + 26 ns t c 2 p clock c2o period 4 t c ? 52 ns 4 t c 4 t c + 52 ns t c 2 h clock c2o high width 2 t c ? 26 ns 2 t c 2 t c + 26 ns t c 2 l clock c2o low width 2 t c ? 26 ns 2 t c 2 t c + 26 ns t f 0 iw f0io width short f0io ? 3 2 t c ? 26 ns 2 t c 2 t c + 6ns long f0io ? 3 4 t c ? 26 ns 4 t c 4 t c + 6ns t stod 2 stio1/2 output delay fom c2o 15 ns 30 ns t stod 4 stio1/2 output delay fom c4io 10 ns 25 ns t f 0 icy cle f0io cycle time 1 half clock adjust 124.975 s 125.000 s 125.025 s 2 half clocks adjust 124.950 s 125.000 s 125.050 s 3 half clocks adjust 124.925 s 125.000 s 125.075 s 4 half clocks adjust 124.900 s 125.000 s 125.100 s ? 1 : time depends on accuracy of clki frequency. because of clock adjustment in the 31st time slot these are the worst case timings when c4io is adjusted. ? 2 : in 8 mbit/s mode the duty cycle of c4io is 1 3 / 2 3 . ? 3 : 170 ns is the minimum value of f0io for s/t data synchronization. smaller values are only allowed if the s/t interface is not used. all speci?cations are for f clk = 24 . 576 mhz. july 2003 data sheet 73 of 94
hfc-s mini cologne chip 6.2.2 slave mode to con?gure the hfc-s mini as pcm / gci / iom2 bus slave bit 0 of the mst_mode0 register must be cleared. in this case c4io and f0io are inputs. table 14: pcm timing values in slave mode symbol characteristics min. max. t c for 2 mb/s (pcm30) 122.07 ns for 4 mb/s (pcm64) 61.035 ns for 8 mb/s (pcm128) 30.518 ns t c 4 p clock c4io period ? 2 t c t c 4 h clock c4io high width 20 ns t c 4 l clock c4io low width 20 ns t c 2 p clock c2o period 4 t c t c 2 h clock c2o high width 2 t c t c 2 l clock c2o low width 2 t c t f 0 is f0io setup time to c4io 20 ns t f 0 ih f0io hold time after c4io 20 ns t f 0 iw f0io width 170 ns t stis stio2 setup time 20 ns t stih stio2 hold time 20 ns ? : if the s/t interface is activated, the frequency must be stable to 10 ? 4 . all speci?cations are for f clk = 24 . 576 mhz. 74 of 94 data sheet july 2003
hfc-s mini cologne chip 7 external circuitries 7.1 s/t interface circuitry in order to comply to the physical requirements of itu-t i.430 recommendation and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the hfc-s mini needs some additional circuitry, which are shown in this section. 7.1.1 external receiver circuitry r15 adj_lev vdd r1 ra1 r20 lev_r1 c15 rb1 rc1 figure 15: external receiver circuitry wake_up_1 and wake_up_2 are for connection to the wake up circuitry (see section 7.1.2 ). c15 and c16 are for reduction of high frequency input noise and should be placed as close as possible to the hfc-s mini . part list vdd 3.3 v 5 v vdd 3.3 v 5 v c15 22pf rd1 4k7 c16 22pf rc1 4k7 c18 47nf rd2 4k7 d2 bav99 rc2 4k7 d1 bav99 r14 680k 1m isdn_st1 isdn connector r15 1m2 1m8 ra2 100k r20 3k9 ra1 100k tr1a s/t module rb1 33k rb2 33k july 2003 data sheet 75 of 94
hfc-s mini cologne chip 7.1.2 external wake-up circuitry the wake-up circuitry is optional. it enables the hfc-s mini to wake up by incoming infox (non info0) signals on the s/t interface. c17 awake gnd (hfc-s mini, pin 28) wake_up_1 r24 r23 (from receiver circuitry) wake_up_2 (from receiver circuitry) r22 q3 figure 16: external wake-up circuitry wake_up_1 and wake_up_2 are inputs from the receiver circuitry. part list part value c17 100pf q3 bc860c r22 4m7 r23 10k r24 100k 76 of 94 data sheet july 2003
hfc-s mini cologne chip 7.1.3 external transmitter circuitry rf2 re1 re2 q6 r18 /tx_en r17 q4 q8 gnd rg2 /tx2_lo vdd isdn_st1 rec1 rec2 trans1 trans2 tx2_hi r19 tx1_hi rf1 r21 r16 gnd gnd /tx1_lo d3 gnd q5 rg1 q7 d4 c14 tr1b trans 16 14 13 1 3 4 d5 * gnd * gnd * 47 pf, optional figure 17: external transmitter circuitry part list vdd 3.3 v 5 v vdd 3.3 v 5 v c14 470pf rf1 18r ? d3 bav99 rf2 18r ? d4 bav99 rg1 3k9 1% 3k 1% d5 2v7 rg2 3k9 1% 3k 1% isdn_st1 isdn connector r16 3k3 q4 bc850c r21 2k2 q5 bc850c r17 50 100 q7 bc850c r18 5k6 q8 bc850c r19 1k8 3k3 q6 bc860c tr1b s/t module re1 560 1% 2k2 1% re2 560 1% 2k2 1% ? : the optional capacitor value depends on the power supply voltage, the used s/t module and the line characteristics. july 2003 data sheet 77 of 94
hfc-s mini cologne chip 7.1.4 s/t modules and transformers customers of cologne chip can chose of a variety of s/t transformers for isdn basic rate interface. all transformers are compatible to the s/t interface of cologne chip?s ?hfc-s? series of that ful?ll two criteria: ? turns ratio of 1:2 (primary side : secondary side) ? center tap on the secondary side (required for cologne chip receiver circuitry) several companies provide transformers and modules that can be used with our isdn basic rate interface controllers. part numbers and manufacturer addresses are listed on cologne chip ?s website http://www.colognechip.com . 78 of 94 data sheet july 2003
hfc-s mini cologne chip 7.2 oscillator circuitry for system clock q1 24.576 mhz c2 r1 c1 r2 clko gnd clki figure 18: oscillator circuitry for s/t clock part list part value r1 330 r2 1m c1 47pf c2 47pf q1 24.576 mhz quartz the values of c1, c2 and r1, r2 depend on the used quartz. for a load-free check of the oscillator frequency the c4o clock of the pcm/gci/iom2 bus should be measured ( hfc-s mini as master, s/t interface deactivated, 4.096 mhz frequency intented on the pin c4io ). figure 19 shows how to connect several hfc-s mini to only one quartz circuitry. gnd gnd r2 330 u1 hfc-s mini 92 91 90 clk_mode osc_out osc_in r1 1m u2 hfc-s mini 92 91 90 clk_mode osc_out osc_in c2 47p u3 hfc-s mini 92 91 90 clk_mode osc_out osc_in r3 330 r4 330 24.576 mhz q1 c1 47p figure 19: cascade-connected hfc-s mini with only one quartz circuitry july 2003 data sheet 79 of 94
hfc-s mini cologne chip 8 state matrices for nt and te 8.1 s/t interface activation / deactivation layer 1 state matrix for nt pending pending state name: reset deactivate activation active deactivation state number: g0 g1 g2 g3 g4 info sent: info 0 info 0 info 2 info 4 info 0 event: state machine release g1 | | | | (note 3) activate request g2 g2 | | g2 (note 1) (note 1) (note 1) deactivate request ? | start timer t2 start timer t2 | g4 g4 expiry t2 (note 2) ? ? ? ? g1 receiving info 0 ? ? ? g2 g1 receiving info 1 ? g2 ? / ? (note 1) receiving info 3 ? / g3 ? ? (note 1, 4) lost framing ? / / g2 ? table 15: activation / deactivation layer 1 for ?nite state matrix for nt legend: ? no state change / impossible by the de?nition of peer-to-peer physical layer procedures or system internal rea- sons | impossible by the de?nition of the physical layer service notes: note 1: timer 1 (t1) is not implemented in the hfc-s mini and must be implemented in software. note 2: timer 2 (t2) prevents unintentional reactivation. its value is 32 ms (256 125 s ). this im- plies that a te has to recognize info 0 and to react on it within this time. note 3: after reset the state machine is ?xed to g0. note 4: bit 7 of the st_wr_sta register must be set every time to allow this transition. the transi- tion is always allowed if bit 0 in sctrl_e is set. 80 of 94 data sheet july 2003
hfc-s mini cologne chip 8.2 s/t interface activation / deactivation layer 1 state matrix for te state name: reset sensing deactivated awaiting signal identifying input synchronized activated lost framing state number: f0 f2 f3 f4 f5 f6 f7 f8 info sent: info 0 info 0 info 0 info 1 info 0 info 3 info 3 info 0 event: state machine release f2 / / / / / / / (note 1) activate request, receiving any signal ? | f5 | | ? | ? receiving info 0 ? | f4 | | ? | ? expiry t3 (note 5) ? / ? f3 f3 ? ? f3 receiving info 0 ? f3 ? ? ? f3 f3 f3 receiving any signal ? ? ? f5 ? / / ? (note 2) receiving info 2 ? f6 f6 f6 f6 ? f6 f6 (note 3) receiving info 4 ? f7 f7 f7 f7 f7 ? f7 (note 3) lost framing (note 4) ? / / / / f8 f8 ? table 16: activation / deactivation layer 1 for ?nite state matrix for te legend: ? no state change / impossible situation | impossible by the de?nition of the layer 1 service notes: note 1: after reset the state machine is ?xed to f 0. note 2: this event re?ects the case where a signal is received and the te has not (yet) determined wether it is info 2 or info 4. note 3: bit- and frame-synchronization achieved. note 4: loss of bit- or frame-synchronization. note 5: timer 3 (t3) is not implemented in the hfc-s mini and must be implemented in software. july 2003 data sheet 81 of 94
hfc-s mini cologne chip 9 binary organization of the frames 9.1 s/t frame structure the frame structures on the s/t interface are different for each direction of transmission. both struc- tures are illustrated in figure 20 . 2 bits offset 48 bits in 250 microseconds d d t 0 1 0 l. . l. . f f l l b1 b1 b1 b1 b1 b1 b1 nt to te te to nt b1 b1 b1 b1 b1 b1 b1 b1 b1 e l. . . d d a l f a f a n l b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 e l. . d d m l b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 e l. . d d s l b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 e l. . . d d l. . l f f l l dc balanced parts of different tes (see note) figure 20: frame structure at reference point s and t legend: f framing bit n bit set to a binary value n = f a (nt to te) l dc balancing bit b1 bit withion b-channel 1 d d-channel bit b2 bit withion b-channel 2 e e-channel bit (echo of d-channel) a bit used for activation f a auxiliary framing bit s s-channel bit m multiframe bit please note ! lines demarcate those parts of the s/t frame that are independently dc-balanced. the fa bit in the direction te to nt is used as q bit in every ?fth frame if s/q bit transmission is enabled (see sctrl register). the nominal 2-bit offset is as seen from the te. the offset can be adjusted with the clkdel register in te mode. the corresponding offset at the nt may be greater due to delay in the interface cable and varies by con?guration. hdlc b-channel data start with the lsb, pcm b-channel data start with the msb. 82 of 94 data sheet july 2003
hfc-s mini cologne chip 9.2 gci frame structure the binary organization of a single gci channel frame is described below. c4io clock frequency is 4096 khz. b7 b7 b7 b6 b6 b6 b5 b5 b5 b4 b4 b4 b3 b3 b3 b2 b1 b2 b2 b1 din f0io c4io dout b2 m time slot 2 dc/i time slot 3 m r m x b1 b1 b1 b1 b0 b0 b0 b1 b2 b4 b3 b2 b1 time slot 0 gci frame time slot 1 time slot 4 time slot 32 figure 21: single channel gci format legend: b1 b-channel 1 data b2 b-channel 2 data m monitor channel data d d-channel data c/i command/indication bits for controlling activation/deactivation and for additional control functions mr handshake bit for monitor channel mx handshake bit for monitor channel july 2003 data sheet 83 of 94
hfc-s mini cologne chip 10 clock synchronization 10.1 clock synchronization in nt-mode receive dpll frame- sync 24.576 mhz s/t - interface pcm interface send dpll clk ab 16384 khz 8192 khz 4096 khz 8 khz 192 khz 8 khz c4io f0io sync_i sync_o divider 24 divider 6, 3, 1.5 sync source select divider select divider 512 2048 1024 divider 4 clk 192 khz (only in slave mode) figure 22: clock synchronization in nt-mode 84 of 94 data sheet july 2003
hfc-s mini cologne chip 10.2 clock synchronization in te-mode receive dpll frame- sync s/t - interface pcm interface 16384 8192 4096 khz 8 khz c4io clk f0io mst- dpll divider select divider select divider 512 2048 1024 divider 4 clk 192 khz 8 khz a a a b b b 24.576 mhz clkdel sync_i sync_o sync source select sync source select 16384 khz 8192 khz 4096 khz (only in slave mode) figure 23: clock synchronization in te-mode the c4io clock is adjusted in the 31th time slot at the gci/iom bus 1..4 times for one half clock cycle. this can be reduced to one adjustment of a half clock cycle (see mst_mode1 register). this is useful if another hfc series isdn controller is connected as slave in nt mode to the pcm bus. the synchronization source can be selected by the mst_mode2 register settings. july 2003 data sheet 85 of 94
hfc-s mini cologne chip 10.3 multiple hfc-s mini synchronization scheme the synchronization scheme for multiple hfc-s mini isdn controllers is shown in figure 24 .the synchronization source of the whole system can be selected by software (see also mst_mode2 register bit description). hfc-s mini hfc-s mini hfc-s mini hfc-s mini sync_i sync_i s/t s/t s/t s/t external frame sync (8 khz) sync_i sync_i sync_o sync_o sync_o sync_o pcm bus slave pcm bus master f0io f0io f0io f0io c4io c4io c4io c4io sync out to other sync inputs figure 24: multiple hfc-s mini synchronization scheme 86 of 94 data sheet july 2003
hfc-s mini cologne chip 11 hfc-s mini package dimensions 0.8 0.05 2.05 0.15 0.10 2.3 unit: mm 10.0 10.0 0.33 0.15 0.75 (0.88) 13.2 13.2 0.2 min 0.1 max max max 0.2 0.2 0.05 0.05 + 0.10 + 0.10 0.3 0.3 0-8 figure 25: hfc-s mini package dimensions july 2003 data sheet 87 of 94
hfc-s mini cologne chip 12 sample circuitries 12.1 s/t interface circuitry (valid in all modes) 1 1 2 2 3 3 4 4 5 5 a a b b c c d d te mode s/t transeiver circuitry for hfc-s mini 1.1 a4 11 friday, july 11, 2003 title size document number rev date: sheet of trans + rec + trans - rec - awake tx2_hi /tx2_lo lev_r1 /tx1_lo lev_r2 r1 adj_lev r2 /tx_en tx1_hi gnd gnd gnd vdd gnd vdd vdd gnd gnd gnd gnd gnd gnd gnd ra2 rb1 rg1 rb2 r15 rc2 r18 r20 r16 r23 d5 rg2 r24 re1 r17 re2 c16 c15 rf1 rf2 r19 r21 rc1 d3 r14 d4 c14 tr1a rec c18 q7 q8 isdn_st1 rj45 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 q4 q5 q6 rd1 d2 c17 c100 optional d1 q3 c101 optional r22 tr1b trans rd2 ra1 figure 26: hfc-s mini sample circuitry 88 of 94 data sheet july 2003
hfc-s mini cologne chip the following bill of materials are related to figure 26 both. they show the component values for 3.3 v or 5 v power supply respectively. bill of materials: s/t transceiver circuitry for 3.3 v power supply revision: 1.1 generated on friday, july 11, 2003 by cologne chip ag (n.b. = not used / not assembled) resistors (25 pcs.) r14 680k r15 1m2 r16 3k3 r17 51 r18 5k6 r19 1k8 r20 3k9 r21 2k2 r22 4m7 r23 10k r24 100k ra1 100k ra2 100k rb1 33k rb2 33k rc1 4k7 rc2 4k7 rd1 4k7 rd2 4k7 re1 560 re2 560 rf1 18 rf2 18 rg1 3k9 rg2 3k9 capacitors (7 pcs.) c14 470p c15 22p c16 22p c17 100p c18 47n c100 optional c101 optional diodes (5 pcs.) d1 bav99 d2 bav99 d3 bav99 d4 bav99 d5 2v7 transistors (6 pcs.) q3 bc858cl q4 bc848cl q5 bc848cl q6 bc858cl q7 bc848cl q8 bc848cl transformers (1 pc.) tr1 s_trans misc (1 pc.) isdn_st1 rj45 total: 25 x resistors 7 x capacitors 5 x diodes 6 x transistors 1 x transformers 1xmisc 45 total + 0 not used / not assembled july 2003 data sheet 89 of 94
hfc-s mini cologne chip bill of materials: s/t transceiver circuitry for 5 v power supply revision: 1.1 generated on friday, july 11, 2003 by cologne chip ag (n.b. = not used / not assembled) resistors (25 pcs.) r14 1m r15 1m8 r16 3k3 r17 100 r18 5k6 r19 3k3 r20 3k9 r21 2k2 r22 4m7 r23 10k r24 100k ra1 100k ra2 100k rb1 33k rb2 33k rc1 4k7 rc2 4k7 rd1 4k7 rd2 4k7 re1 2k2 re2 2k2 rf1 18 rf2 18 rg1 3k rg2 3k capacitors (7 pcs.) c14 470p c15 22p c16 22p c17 100p c18 47n c100 optional c101 optional diodes (5 pcs.) d1 bav99 d2 bav99 d3 bav99 d4 bav99 d5 2v7 transistors (6 pcs.) q3 bc858cl q4 bc848cl q5 bc848cl q6 bc858cl q7 bc848cl q8 bc848cl transformers (1 pc.) tr1 s_trans misc (1 pc.) isdn_st1 rj45 total: 25 x resistors 7 x capacitors 5 x diodes 6 x transistors 1 x transformers 1xmisc 45 total + 0 not used / not assembled 90 of 94 data sheet july 2003
hfc-s mini cologne chip 12.2 hfc-s mini in mode 2 (motorola bus) figure 27 shows only the processor part of a hfc-s mini sample board in mode 2 (motorola). the s/t interface circuitry shown in figure 26 must be enclosed to complete the sample board. 1 1 2 2 3 3 4 4 5 5 a a b b c c d d to motorola processor interface hfc-s mini in mode 2 processor interface signals 1.1 motorola bus with control signals /cs,r/w,/ds a4 11 friday, july 11, 2003 title size document number rev date: sheet of d6 f1_a d1 /cs /ds wake_up d5 d3 d7 /ds d4 d4 /res sync_i f1_b d2 d5 r/w d7 d2 d6 a0 /cs d0 /tx2_lo f0io r/w c4io stio1 d3 adj_lev d0 tx2_hi /tx_en /tx1_lo d1 r2 /int r1 stio2 tx1_hi /wait lev_r2 a0 sync_o lev_r1 /int gnd gnd gnd gnd vdd gnd gnd gnd vdd u1a hfc-s mini 26 27 38 43 4 5 6 7 8 9 10 11 47 1 2 36 45 44 46 48 28 25 23 22 21 20 17 16 15 14 13 34 35 32 33 31 30 clki clko sync_i sync_o d0 d1 d2 d3 d4 d5 d6 d7 a0 ds rw wait ale int cs res awake adj_lev r1 lev_r1 lev_r2 r2 tx1_hi tx2_lo tx_en tx1_lo tx2_hi f1_a f1_b stio1 stio2 f0io c4io u1b hfc-s mini 12 18 24 29 37 39 41 3 19 40 gnd gnd gnd gnd gnd gnd gnd vdd vdd vdd jp1 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 c4 33n c5 33n c6 33n c2 33p c1 33p + c3 10 24.576 q1 r1 330 r2 1m figure 27: hfc-s mini sample circuitry in processor mode 2 (motorola) july 2003 data sheet 91 of 94
hfc-s mini cologne chip 12.3 hfc-s mini in mode 3 (intel bus with separate address bus/data bus) figure 28 shows only the processor part of a hfc-s mini sample board in mode 2 (motorola). the s/t interface circuitry shown in figure 26 must be enclosed to complete the sample board. 1 1 2 2 3 3 4 4 5 5 a a b b c c d d to intel non multiplexed processor interface hfc-s mini in mode 3 processor interface signals 1.1 intel bus with seperated adress and data bus, control signals /cs,/wr,/rd a4 11 friday, july 11, 2003 title size document number rev date: sheet of tx2_hi r1 lev_r2 /tx_en tx1_hi /tx1_lo /tx2_lo r2 adj_lev wake_up lev_r1 f1_a f1_b sync_o /int /wait stio1 stio2 f0io c4io d1 d2 d3 d4 d5 d6 d7 d0 sync_i a0 /rd /cs /res /wr d7 d3 d6 d5 d2 d4 d1 d0 /rd /wr /cs a0 /int gnd gnd gnd gnd gnd vdd gnd gnd gnd u1a hfc-s mini 26 27 38 43 4 5 6 7 8 9 10 11 47 1 2 36 45 44 46 48 28 25 23 22 21 20 17 16 15 14 13 34 35 32 33 31 30 clki clko sync_i sync_o d0 d1 d2 d3 d4 d5 d6 d7 a0 rd wr wait ale int cs res awake adj_lev r1 lev_r1 lev_r2 r2 tx1_hi tx2_lo tx_en tx1_lo tx2_hi f1_a f1_b stio1 stio2 f0io c4io u1b hfc-s mini 12 18 24 29 37 39 41 3 19 40 gnd gnd gnd gnd gnd gnd gnd vdd vdd vdd jp1 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 c4 33n c5 33n c6 33n c2 33p c1 33p + c3 10 24.576 q1 r1 330 r2 1m figure 28: hfc-s mini sample circuitry in processor mode 3 (intel), 1st part 92 of 94 data sheet july 2003
hfc-s mini cologne chip 12.4 hfc-s mini in mode 4 (intel bus with multiplexed address bus/data bus) figure 29 shows only the processor part of a hfc-s mini sample board in mode 2 (motorola). the s/t interface circuitry shown in figure 26 must be enclosed to complete the sample board. 1 1 2 2 3 3 4 4 5 5 a a b b c c d d to intel multiplexed processor interface processor interface signals hfc-s mini in mode 4 1.1 intel bus with multiplexed address and data bus a4 11 friday, july 11, 2003 title size document number rev date: sheet of c4io d1 f0io d0 tx1_hi d7 f1_b /int lev_r2 d5 f1_a /wr stio2 d1 sync_o sync_i lev_r1 r1 d6 ale /tx_en d6 /cs /rd wake_up d3 /cs stio1 d5 d2 r2 /wr adj_lev /wait tx2_hi /int d4 d0 d4 /tx2_lo d3 /tx1_lo /res d7 d2 /rd ale gnd vdd gnd gnd gnd gnd gnd gnd gnd u1a hfc-s mini 26 27 38 43 4 5 6 7 8 9 10 11 47 1 2 36 45 44 46 48 28 25 23 22 21 20 17 16 15 14 13 34 35 32 33 31 30 clki clko sync_i sync_o d0 d1 d2 d3 d4 d5 d6 d7 a0 rd wr wait ale int cs res awake adj_lev r1 lev_r1 lev_r2 r2 tx1_hi tx2_lo tx_en tx1_lo tx2_hi f1_a f1_b stio1 stio2 f0io c4io u1b hfc-s mini 12 18 24 29 37 39 41 3 19 40 gnd gnd gnd gnd gnd gnd gnd vdd vdd vdd jp1 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 c4 33n c5 33n c6 33n c2 33p c1 33p + c3 10 24.576 q1 r1 330 r2 1m figure 29: hfc-s mini sample circuitry in processor mode 4 (intel, multiplexed), 1st part july 2003 data sheet 93 of 94
cologne chip ag data sheet of hfc-s mini cologne chip

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